• 제목/요약/키워드: Chip Flow

검색결과 315건 처리시간 0.027초

반도체 칩 캡슐화 공정의 최적조건에 관한 연구 (A Study on Optimal Process Conditions for Chip Encapsulation)

  • 허용정
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1995년도 춘계학술대회 논문집
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    • pp.477-480
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    • 1995
  • Dccisions of optimal filling conditions for the chip encapsulation have been done primarily by an ad hoc use of expertise accumulated over the years because the chip encapsulation process is quite complicated. The current CAE systems do not provide mold designers with necessary knowledge of the chip encapsulation for the successful design of optimal filling except flow simulation capability. There have been no attempts to solve the optimal filling problem in the process of the chip encapsulation. In this paper, we have constructed an design system for optimal filling to avoid short shot in the chip encapsulation process which combines an optimization methodology with CAE software.

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절삭가공시 집형성의 유한요소 해석에 관한 연구 (A Study on the Finite Element Analysis of Chip Formation in Machining)

  • 김남용;박종권;이동주
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1997년도 추계학술대회 논문집
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    • pp.973-976
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    • 1997
  • Process behavior in metal cutting results from the chip formation process which is not easily observable and measurable during machining. By means of the finite element method chip formation in orthogonal metal cutting is modeled. The reciprocal interaction between mechanical and thermal loads is taken into consideration by involving the thermo-viscoplastic flow behavior of workpiece material. Local and temporal distributions of stress and temperature in the cutting zone are calculated depending on the cutting parameters. The calculated cutting forces and temperatures are compared with the experimental results obtarned from orthogonal cutting of steel AISl 4140. The model can be applied in process design for selection of appropriate tool-workpiece combination and optimum cutting conditions in term of mechanical and thermal loads.

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랩온어칩 내부 미세유동 제어를 위한 새로운 장치의 개발 및 적용 (Development of A New Device for Controlling Infinitesimal Flows inside a Lab-On-A-Chip and Its Practical Application)

  • 김보람;김국배;이상준
    • 유체기계공업학회:학술대회논문집
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    • 유체기계공업학회 2006년 제4회 한국유체공학학술대회 논문집
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    • pp.305-308
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    • 2006
  • For controlling micro-flows inside a LOC (lab-on-a-chip) a syringe pump or an electronic device for EOF(electro-osmotic flow) have been used in general. However, these devices are so large and heavy that they are burdensome in the development of a portable micro-TAS (total analysis system). In this study, a new flow control system employing pressure chambers, digital switches and speed controllers was developed. This system could effectively control the micro-scale flows inside a LOC without any mechanical actuators or electronic devices We also checked the feasibility of this new control system by applying it to a LOC of micro-mixer type. Performance tests show that the developed control system has very good performance. Because the flow rate in LOC is controlled easily by throttling the speed controller, the flows in complicate microchannels network can be also controlled precisely.

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신경망기법에 의한 칩브레이커의 성능평가 (Performance Evaluation of Chip Breaker Utilizing Neural Network)

  • 김홍규;심재형
    • 한국공작기계학회논문집
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    • 제16권3호
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    • pp.64-74
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    • 2007
  • The continuous chip in turning operation deteriorates precision of workpiece and causes a hazardous condition to operator. Thus the chip form control becomes a very important task for reliable machining process. So, grooved chip breaker is widely used to obtain reliable discontinuous chip. However, developing new cutting insert having chip breaker takes long time and needs lots of research expense due to a couple of processes such as forming, sintering, grinding and coating of product and many different evaluation tests. In this paper, performance of commercial chip breaker is evaluated with neural network which is learned with a back propagation algorithm. For the evaluation, several important elements(depth of cut, land, breadth, radius) which directly influence the chip formation were chosen among commercial chip breakers and were used as input values of neural network. With the results of these input values, the performance evaluation method was developed and applied that method to the commercial tools.

A Low Power Analog CMOS Vision Chip for Edge Detection Using Electronic Switches

  • Kim, Jung-Hwan;Kong, Jae-Sung;Suh, Sung-Ho;Lee, Min-Ho;Shin, Jang-Kyoo;Park, Hong-Bae;Choi, Chang-Auck
    • ETRI Journal
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    • 제27권5호
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    • pp.539-544
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    • 2005
  • An analog CMOS vision chip for edge detection with power consumption below 20mW was designed by adopting electronic switches. An electronic switch separates the edge detection circuit into two parts; one is a logarithmic compression photocircuit, the other is a signal processing circuit for edge detection. The electronic switch controls the connection between the two circuits. When the electronic switch is OFF, it can intercept the current flow through the signal processing circuit and restrict the magnitude of the current flow below several hundred nA. The estimated power consumption of the chip, with $128{\times}128$ pixels, was below 20mW. The vision chip was designed using $0.25{\mu}m$ 1-poly 5-metal standard full custom CMOS process technology.

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네오디뮴 영구자석을 이용한 컨베이어벨트 구동형 미세칩 포집장치의 성능 평가 (Performance Evaluation of Microchip Removal Device Rotating by Conveyor Belt with Neodymium Permanent Magnet)

  • 최성윤;왕준형;왕덕현
    • 한국기계가공학회지
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    • 제20권1호
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    • pp.103-109
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    • 2021
  • Fine chips generated by machining have an impact on machine failure and quality of machined products, it is necessary to remove the chips, so the microchip collection and removal device by rotating conveyor belt with neodymium permanent magnets was developed. In this research, to solve the problem for reducing the existing microchips in the tank, a micro-chip removal device by rotating conveyor belt with neodymium permanent magnets developed. In the development of micro-chip removal device, 3D CATIA modeling was used, and the flow analysis and the electromagnetic force analysis were performed with COMSOL Multiphysics program. To evaluate the performance of the prototypes produced, design of experiments (DOE) is used to obtain the effect of neodymium conveyor movement speed on chip removal for the ANOVA analysis of recovered powders. An experiment was conducted to investigate the effect of the conveyor feed rate on the chip removal performance in detail. As a result of the experiment, it was confirmed that the slower the feeding speed of the fine chip removing device, the more efficient the chip removal.

디지털 비디오 방송 컴플라이언트 위성 수신 칩의 Physical 설계 및 검증 (Physical Design Flow & Verification of DVB Compliant Satellite Receiver Chip)

  • 신수경;최영식
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2001년도 춘계종합학술대회
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    • pp.345-348
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    • 2001
  • 본 논문은 디지털 비디오 방송 컴플라이언트 위성 수신칩에 대한 physical 설계 순서 및 검증에 대한 설계 기술에 관한 것으로서 각각의 설계 순서에 대한 고찰 및 문제점 그리고 물리적 레이아웃에 대한 검증 과정과 그 결과에 대하여 기술하였다.

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Effect of Chip Spacing in a Multichip Module on the Heat Transfer for Paraffin Slurry Flow

  • Choi, Min-Goo;Cho, Keum-Nam
    • Journal of Mechanical Science and Technology
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    • 제14권9호
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    • pp.997-1004
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    • 2000
  • The experiments were conducted by using water and paraffin slurry to investigate the effect of a chip spacing in the multichip module on the cooling characteristics from an in-line $4{\times}3$ array of discrete heat sources which were flush mounted on the top wall of a channel. The experimental parameters were chip spacing in a multichip module, heat flux of simulated VLSI chip, mass fraction of paraffin slurry, and channel Reynolds number. The removable heat flux at the same chip surface temperature decreased as the chip spacing decreased at the first and fourth rows. The local heat transfer coefficients for the paraffin slurry were larger than those for water, and the chip spacing on the local heat transfer coefficients for paraffin slurry influenced less than that for water. The enhancement factor for paraffin slurry showed the largest value at a mass fraction of 5% regardless of the chip spacing, and the enhancement factors increased as the chip spacing decreased. This means that the paraffin slurry is more effective than water for cooling of the highly integrated multichip module.

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Explaining Dividend Payout: Evidence from Malaysia's Blue-Chip Companies

  • CHE-YAHYA, Norliza;ALYASA-GAN, Siti Sarah
    • The Journal of Asian Finance, Economics and Business
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    • 제7권12호
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    • pp.783-793
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    • 2020
  • This research investigates the explanatory factors governing the dividend payout to shareholders of blue-chip companies listed on Bursa Malaysia. In spite of continuous attention offered by empirical research on dividend payout of publicly-listed companies, paradoxically only few studies exclusively examined the explanatory factors from the perspective of blue-chip companies. Recognizing the capability of blue-chip companies to serve as a stalwart indicator of stock market condition as well as a consistent income source to shareholders, more research should be carried out for better inference on the companies' dividend payout decision. This research is using 522 observations from a sample of 18 Malaysian blue-chip companies over a 29-year period (1990 to 2019) and utilizes a panel data regression analysis for the estimation of the impact of eight factors, namely, systematic risk, leverage, free cash flow, lagged dividends, market-to-book value, profit growth, total asset turnover, and company size. Measuring dividend payout using two specifications (dividend/earnings and dividend/total assets), this research reveals that systematic risk and free cash flow have a significant and negative impact on dividend payout. Meanwhile, past year dividends, market-to-book value, profit growth, total asset turnover and company size have a significant and positive impact on dividend payout.

고전류 스트레싱이 금스터드 범프를 이용한 ACF 플립칩 파괴 기구에 미치는 영향 (High Electrical Current Stressing Effects on the Failure Mechanisms of Austudbumps/ACFFlip Chip Joints)

  • 김형준;권운성;백경욱
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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    • pp.195-202
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    • 2003
  • In this study, failure mechanisms of Au stud bumps/ACF flip chip joints were investigated underhigh current stressing condition. For the determination of allowable currents, I-V tests were performed on flip chip joints, and applied currents were measured as high as almost 4.2Amps $(4.42\times10^4\;Amp/cm^2)$. Degradation of flip chip joints was observed by in-situ monitoring of Au stud bumps-Al pads contact resistance. All failures, defined at infinite resistance, occurred at upward electron flow (from PCB pads to chip pads) applied bumps (UEB). However, failure did not occur at downward electron flow applied bumps (DEB). Only several $m\Omega$ contact resistance increased because of Au-Al intermetallic compound (IMC) growth. This polarity effect of Au stud bumps was different from that of solder bumps, and the mechanism was investigated by the calculation of chemical and electrical atomic flux. According to SEM and EDS results, major IMC phase was $Au_5Al_2$, and crack propagated along the interface between Au stud bump and IMC resulting in electrical failures at UEB. Therefore. failure mechanisms at Au stud bump/ACF flip chip Joint undo high current density condition are: 1) crack propagation, accompanied with Au-Al IMC growth. reduces contact area resulting in contact resistance increase; and 2) the polarity effect, depending on the direction of electrons. induces and accelerates the interfacial failure at UEBs.

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