• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.751-754
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• 1998

This research aims at developing a single chip multiprocessor for high-performance computer system. Our design approach is to design a relatively small and simple processor unit and to integrate multiple copies of the unit in an efficient way. The proposed multiprocessor is composed of four CPUs and one graphic coprocessor. The four CPUs share the graphic coprocessor and each CPU implements the 64-bit SPARC-V9 instruction set architecture. This paper gives an overview of the proposed microarchitecture and discusses the considerations made in the course of the design.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.6
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• pp.793-798
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• 2011

In this study, it was grasped to the flow characteristics of cutting fluid injected by nozzle installed in high pressure holder for avoiding chip curling occurred during machining process. And for avoiding chip curling, the possibility of elimination under various chip conditions was checked. Consequently, the highest discharging pressure and velocity was shown in 150 of nozzle inflow angle. Also as nozzle outlet diameter is small, the pressure and velocity of injected flow are high. Moreover, It could be confirmed that width and thickness of chip have no direct effect on chip elimination and it is achieved by torque generated by injected cutting fluid.

• Journal of the Korean Society of Safety
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• v.16 no.2
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• pp.22-26
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• 2001

The machining process on be considered as a planned interaction of the workpiece, the tool and the machine tool. In an unmanned situation, the results of this interaction are to be continuously monitored so that any changes in the machining environment on be sensed to corrective actions. In order to design the process monitoring system for unmanned manufacturing, the identification of chip formation is proposed. The system proposes the method of using acoustic emission(AE) signal analysis to identify the chip formation during cutting.

• Journal of the Korean Society for Precision Engineering
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• v.12 no.9
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• pp.148-155
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• 1995

The object of this study is to achieve a gteater understanding of meterial removal process and its mechanism. In this study, some applications of finite element techniques are applied to analyze the chip formation and cutting heat generation mechanism of metal cutting. To know the effect of cutting parameters, simulations employed some independent cutting variables change, such as constitutive deformation laws of workpiece and tool material, frictional coefficients and tool-chip contact interfaces, cutting speed, tool rake angles, depth of cut and this simulations also include large elastic-plastic defor- mation, adiabetic thermal analysis. Under a usual plane strain assumption, quasi-static, thermal-mechanical coupling analysis generate detailed informations about chip formation process and cutting heat generation mechanism Some cutting parameters are affected to cutting force, plastic deformation of chip, shear plane angle, chip thickness and tool-chip contact length and reaction force on tool, cutting temperature and thermal behavior. Several aspects of the metal cutting process predicted by the finite element analysis provide information about tool shape design and optimal cutting conditions.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.497-500
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• 2005

This paper presents a design of a hybrid sensor chip which integrates an A/D converter module and a phase measurement module for measuring power line phase. Recursive sliding DFT based phase measurement module is designed using time shared multiplier which can reduce the size of SoC implementation. A/D converter is based on the sigma delta modulation in order to minimize the implementation space of the analog part and designed to obtain 8-bit resolution. Computer simulations and FPGA implementation are performed to verify hybrid sensor chip design. The hybrid sensor chip for 4-channel power line phase measurement is fabricated by using 0.35 micrometer CMOS process.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.1-6
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• 2017

As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.9 no.2
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• pp.72-79
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• 2000

A new optimal tool design model which can be minimized the resultant cutting forces under the constrains of variables was developed. The resultant cutting forces are used as the objective function and tool angles are used as the variables. Cutting experiments of tool wear and chip length using the new and conventional tools wee carried out. Tool life of optimized cutter are more increased than those of conventional cutter by 2.29 times and 2.52 times at light and at heavy cutting conditions respectively. Chip length of optimized cutter are more increased than those of conventional cutter It is considered that the decrease of the resultant cutting forces is the cause that an effective rake and shear angles by the shape of optimal cutter.

• Proceedings of the KIEE Conference
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• 2000.07a
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• pp.215-217
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• 2000

Protective relay play a crucial role in the proper operation of a power system, and the reliable transfer of electrical power. This paper deals with the design and implementation of a digital protective relay on a single chip. Implementation on the FPGA(Field Programmable Gate Array) of the chip of digital protective relay. This protective relaying chip monitors the frequency and the voltage and current of the power system. And report the voltage, the current. the frequency, active power and reactive power.

• Journal of the Semiconductor & Display Technology
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• v.12 no.1
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• pp.53-59
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• 2013

Chip mounter which is used to pick chips from the pre-specified position and place them on the target location of PCB is an essential device in semiconductor and LCD industries. Quick and high precision positioning is the key technology needed to increase productivity of chip mounters. As increasing acceleration and deceleration of placing motion, structural vibration induced from inertial reactive force and flexibility of mounter structure becomes a serious problem degrading positioning accuracy. Motivated from these, this paper proposed a new control design algorithm which combines a mounter structure acceleration feedforward compensation and an extended sliding mode control for fine positioning and suppression of structural vibration, simultaneously. The feasibility of the proposed control design was verified along with some simulation results.