• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.271-275
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• 1995

Chip control is a major problem in automatic machining process, especially in finish operation. Chip breaker is one of the important factors to be determined for the scheme of chip control. As unbroken chips are grown, there deteriorate quality of the surface roughness and process automation can be carried out. In this study, to get rid of chip curling problem while turning internal hole, optimal chip breaker is selected form the experiment. The experiment is planned with Taguchi's method that is based on the orthogonal arrary of design factor. From the respose table, cutting speed, feedrate, depth of cut, and tool geometry are major factors affecting chip formation. Then, optmal chip breaker is selected and this is verified good enough for chip control from the experiment.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.04a
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• pp.251-254
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• 2004

Web-Bioconductor System은 유전자 분석에 대한 통계적 모듈과 그래픽 환경을 제공하는 R언어와 DNA chip 데이터의 분석을 수행하는 Bioconductor 패키지를 이용하여 웹으로 DNA chip 데이터를 분석할 수 있도록 설계한 시스템이다. 본 시스템은 DNA chip 데이터의 분석을 위해 사용자 계정 모듈, 데이터 입력 모듈, 전 처리 모듈, 유전자 차등 발현 분석 모듈, 결과 출력 모듈로 구성되어 있으며, 분석된 결과물은 HTML, 이미지, XLS 파일 형태로 제공된다. 웹을 이용하여 DNA chip 분석을 수행함으로써 인터넷이 가능한 곳이면 시간과 장소의 구분이 없이 DNA chip 데이터 분석이 가능하며, 인터넷으로 DNA chip 데이터 분석 자료를 공유할 수 있음으로 연구자들의 상호 의견 교환을 바탕으로 효율적인 분석이 가능할 것이다. 또한 기존의 R언어와 Bioconductor가 전산 지식이 부족한 사람들에게는 접근하기 어려운 점을 웹 인터페이스로 간단하게 구현함으로써 DNA chip 데이터 분석에 있어 용이성과 효율성을 중대하고 있다.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.103-106
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• 2005

This paper reports design and fabrication of CMOS temperature sensor circuit using MOSIS 0.25um CMOS technology. The proposed circuit has a temperature coefficient of $13mV/^{\circ}C$ for a wide operating temperature range with a good linearity. This circuit may be applicable to the design of one-chip IC where quartz crystal resonator is directly mounted on CMOS oscillator chips.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.567-570
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• 1988

This paper describes the design of FIR filtering DSP-chip that can be operated without programming. The proposed DSP-chip has not only the improvement of execution time but also selectivity of filter length from N=1 to N=128. Hilbert Transformer can be designed from this chip. FIR filter system is composed of Data memory/Control Unit, external memory and multiplier-accumulator. Data memory/Control Unit is laid out in this paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.888-889
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• 2015

This paper presents a method of constructing the system-on-chip(SoC) based on embedded systems. The proposed method is more compact and effectiveness than former methods. The requirements generation start high level performance simulation and then passes to an executable specification suitable for implementation using a hardware/software co-design tool. The reuse of pre-exiting components is supported, as well as synthesis of the system interface, but only after much work is done to program the hardware/software co-design tool. The actual design flow described allows feedback among all design levels, e.g. from implementation up to requirements, throughout the process. In the future, it is necessary to development the advanced method of constructing system-on-chip based on embedded systems.

• The Research Journal of the Costume Culture
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• v.20 no.6
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• pp.869-882
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• 2012

The purpose of this study is to obtain the patent for extracting the color map and color chip from the color image source and to develop color image map for fashion design. For this study, fashion image maps were produced from 210 pictures with Adobe Photoshop CS2 program targeting 200 university students from 2004 to 2006. The procedures for extracting the color map and color chip included providing the color image, the filtering phase, the segmentation phase, the extraction phrase, and the arrangement phase. Based on the results of this study, patent application was made to KIPO(Korean Intellectual Property Office) for this invention. The following effects can be expected from the standpoint of design based on the case study. First, it is a straight forward procedure to extract a color chip and color map from a color image. Second, it can be applied to various art works based on the recombination of colors as representative colors can be extracted from the related color image that combines a variety of colors. Third, desired colors can be selected based on the taste cluster classification or sensibility axis of design by extracting the representative color from the color image.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.180-188
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• 2015

As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/µm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/µm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.832-841
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• 2016

The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.4
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• pp.147-153
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• 2012

The demands of the large scale machine tools, for instance, such as planomiller, turning machine, boring machine, NC machine, have been gradually increased in recent years. As the performances of machine tools and/or cutting tools are advanced, it is possible to perform high-speed and high-precision cutting works. The effective treatment of wet chip, which is discharged from cutting works, becomes very important problems. Therefore, this study is forced on the design of large scale machine tools using CATIA V5R18 and analysis of cutter, which is considered as essential equipment in large scale machine tools, using MSC.Nastran & MSC.Patran. Especially, the relations between tolerated load of cutter, driving horse power and rpm of driving shaft in chip processing system are investigated through analysis. As the results, the reliability of design could be improved by evaluating simulated numerical values, it showed that tolerated loads of supported part and edged part of cutter are 87,000N and 14,450N, respectively.