• Proceedings of the Safety Management and Science Conference
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• 2002.05a
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• pp.207-214
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• 2002

This paper presents some physical evidences indicating that reduced friction occurs in an cryogenic machining process, in which LN2 is applied selectively in well-controlled jets to the selected cutting zone. In machining tests, cryogenic machining reduced the force component in the feed direction, indicating that the chip slides on the tool rake face with lower friction. This study also found that the effectiveness of LN2 lubrication depends on the approach how LN2 is applied regarding cutting forces related.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.37 no.1
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• pp.75-79
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• 2013

Demands for semiconductor devices are dramatically increasing, and advancements in fabrication technology are allowing a step-up in the number of devices per unit area. As a result, semiconductor devices require higher heat dissipation, and thus, cooling solutions have become important for guaranteeing their operational reliability. In particular, in chip-in-board packages, in which chips and passives are embedded in the substrates for efficient device layout, heat dissipation is of greater importance. In this study, a thermal model for layers of different materials has been proposed, and then, the heat transfer has been simulated by imposing a set of appropriate boundary conditions. Heat generation can be predicted based on the results, which will be utilized as practical data for actual package design.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.12
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• pp.540-551
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• 2008

Today's microprocessor designs are not free from temperature as well as power consumption. As processor technology scales down, an on-chip circuitry increases power density, which incurs excessive temperature (hotspot) problem. To tackle thermal problems cost-effectively, Dynamic Thermal Management (DTM) has been suggested: DTM techniques have benefits of thermal reliability and cooling cost. However, they require trade-off between thermal control and performance loss. This paper proposes a dual integer register file structure to minimize the performance degradation due to DTM invocations. In on-chip thermal control, the most important functional unit is an integer register file. It is the hotspot unit because of frequent read and write data accesses. The proposed dual integer register file migrates read data accesses by adding an extra register file, thus reduces per-unit dynamic power dissipation. As a result, the proposed structure completely eliminates localized hotspots in the integer register file, resulting in much less performance degradation by average 13.35% (maximum 18%) improvement compared to the conventional DTM architecture.

• Journal of the Korea Society of Computer and Information
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• v.16 no.7
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• pp.1-11
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• 2011

Many researchers have studied on the methods to improve the processor performance. However, high integrated semiconductor technology for improving the processor performance causes many problems such as battery life, high power density, hotspot, etc. Especially, as hotspot has critical impact on the reliability of chip, thermal problems should be considered together with performance and power consumption when designing high-performance processors. To alleviate the thermal problems of processors, there have been various researches. In the past, mechanical cooling methods have been used to control the temperature of processors. However, up-to-date microprocessors causes severe thermal problems, resulting in increased cooling cost. Therefore, recent studies have focused on architecture-level thermal-aware design techniques than mechanical cooling methods. Even though architecture-level thermal-aware design techniques are efficient for reducing the temperature of processors, they cause performance degradation inevitably. Therefore, if the mechanical cooling methods can manage the thermal problems of processors efficiently, the performance can be improved by reducing the performance degradation due to architecture-level thermal-aware design techniques such as dynamic thermal management. In this paper, we analyze the cooling efficiency of high-performance multicore processors according to mechanical cooling methods. According to our experiments using air cooler and liquid cooler, the liquid cooler consumes more power than the air cooler whereas it reduces the temperature more efficiently. Especially, the cost for reducing $1^{\circ}C$ is varied by the environments. Therefore, if the mechanical cooling methods can be used appropriately, the temperature of high-performance processors can be managed more efficiently.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.881-887
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• 2014

Micro-sized Peltier coolers are generally employed for uniformly distributing heat generated in the multi-chip packages. These coolers are commonly classified into vertical and planar devices, depending on the heat flow direction and the arrangement of thermoelectric materials on the used substrate. Owing to the strong need for evaluation of performance of thermoelectric modules, at present an establishment of proper theoretical model has been highly required. The design theory for micro-sized thermoelectric cooler should be considered with contact resistance. Cooling performance of these modules was significantly affected by their contact resistance such as electrical and thermal junction. In this paper, we introduce the useful and optimal design model of small dimension thermoelectric module.

• Journal of Advanced Marine Engineering and Technology
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• v.34 no.8
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• pp.1100-1106
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• 2010

LED(Light Emitting Diode) has the defects of low efficiency and reducement of life cycle as its temperature increases. This research is about an efficient temperature control of the LED. For LED temperature control, it is shown that a heat sink, fan, a one-chip microprocessor and the PID control algorithm are a good cooling system through experiments. Finally. by using the fan as a cooling device and controlling it appropriately, it is proved that the intensity of illumination and the desired temperature can be achieved with consumption of only 2% of the driving power of the LED system through control experiments.

• Proceedings of the KIEE Conference
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• 2000.11c
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• pp.586-588
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• 2000

본 논문은 전자 패키징의 방열 성능을 개선하기 위하여 초소형 히트 파이프를 제작하고 열전달 성능을 시험한 결과를 보여준다. IC 칩이 점점 고성능화되고 고집적화되어 감에 따라 발열 문제가 대두되는데, 이 열은 전도만으로는 충분히 소산시킬 수 없고 패키징 표면에 별도의 장치를 장착하는 것은 시스템 소형화의 장애 요소가 된다. 따라서, 고성능 칩 개발을 위한 선결 과제로 고성능 초소형 냉각 장치가 요구되고 있다. 히트파이프는 밀봉된 파이프 내의 2상 유동과 상변화 잠열을 이용하여 열원으로부터 히트 싱크로 열을 효과적으로 전달하는 열교환 장치이다. 본 논문에서는 전자 패키징 내에 집적화할 수 있도록 초소형 히트 파이프 어레이를 제작하여 그 성능을 시험한 결과 증발부의 온도가 $12.1^{\circ}C$ 감소됨을 보인다.

• Journal of Astronomy and Space Sciences
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• v.17 no.1
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• pp.53-66
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• 2000

We developed low light CCD imaging system using thermoelectric cooling method collaboration with a company to design a commercial model. It consists of Kodak KAF-0401E(768$\times$512 pixels) CCD chip, thermoelectric module manufactured by Thermotek. This TEC system can reach an operative temperature of $-25^{\circ}C$. We employed an Uniblitz VS25s shutter and it has capability a minimum exposure time 80ms. The system components are an interface card using a Korea Astronomy Observatory (hereafter KAO) ISA bus controller, image acquisition with AD9816 chip, that is 12bit video processor. The performance test with this imaging system showed good operation within the initial specification of our design. It shows a dark current less than 0.4e-/pixel/sec at a temperature of $-10^{\circ}C$, a linearity 99.9$\pm$0.1%, gain 4.24e-/adu, and system noise is 25.3e-(rms). For low temperature CCD operation, we designed a TEC, which uses a one-stage peltier module and forced air heat exchanger. This TEC imaging system enables accurate photometry($\pm$0.01mag) even though the CCD is not at 'conventional' cryogenic temperatures(140k). The system can be a useful instrument for any other imaging applications. Finally, with this system, we obtained several images of astronomical objects for system performance tests.

• Tribology and Lubricants
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• v.5 no.1
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• pp.44-50
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• 1989

High strength steel is similar to carbon steel in its composition. This material is developed originally for special uses such as aerospace and automobile due to its high strength and shock-free property in spite of lightness. But the chemical attraction of high strength steel is serious, which includes comminution of formation, metalization and strengthening. Machining results in built-up edge between this material and the tool. Especially the work hardening behavior results in tool life shortening, which was caused by temperature generation during machining. In this study, cooling system was made in which liquid nitrogen is supplied to circulate in order to make up for these weaknesses. Machining of high strength steels, which is recognized as difficult to machine materials, was conducted after tool is cooled at -195$\circ$C. Experimental results showed that the tool was cooled down rapidly below -195$\circ$C in about 200 seconds. The tool temperature of machining with cooling system was lowered by 60~95$\circ$C than that of machining in room temperature. The hardness of the surface of chip is decreased by machining with cooling system. And the machining using the cooling system made it possible to increase shear angle, to retain smooth surface on chip without built-up-edge and to get a better roughness.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.2
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• pp.61-67
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• 2003

The interfacial reaction between ultra-small 58Bi-42Sn solder and Au/Ni/Ti under bump metallurgy (UBM) for ultra-fine flip chip application was investigated. The ultra-small 58Bi-42Sn solder bump, about $46{\mu}m$ in diameter, was fabricated by using the lift-off method and reflowed using the rapid thermal annealing (RTA) system. The intermetallic compounds were characterized using a secondary electron microscopy (SEM), an energy dispersive spectroscopy (EDS), and an x-ray diffractometer (XRD). The faceted and polygonal intermetallic compounds were found in the Bi-Sn solder bumps on $Au(0.1{\mu}m)/Ni/Ti$ UBM and they were indentified as $(Au_xBi_yNi_{1-x-y})Sn_2$ Phase. The intermetallic compounds grown from the $Au(0.1{\mu}m)/Ni/Ti$ UBMinterface were dispersed in the solder bump.