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http://dx.doi.org/10.9708/jksci.2011.16.7.001

Analysis on the Cooling Efficiency of High-Performance Multicore Processors according to Cooling Methods  

Kang, Seung-Gu (School of Electronics and Computer Engineering, Chonnam National University)
Choi, Hong-Jun (School of Electronics and Computer Engineering, Chonnam National University)
Ahn, Jin-Woo (School of Electronics and Computer Engineering, Chonnam National University)
Park, Jae-Hyung (School of Electronics and Computer Engineering, Chonnam National University)
Kim, Jong-Myon (School of Computer Engineering and Information Technology, University of Ulsan)
Kim, Cheol-Hong (School of Electronics and Computer Engineering, Chonnam National University)
Abstract
Many researchers have studied on the methods to improve the processor performance. However, high integrated semiconductor technology for improving the processor performance causes many problems such as battery life, high power density, hotspot, etc. Especially, as hotspot has critical impact on the reliability of chip, thermal problems should be considered together with performance and power consumption when designing high-performance processors. To alleviate the thermal problems of processors, there have been various researches. In the past, mechanical cooling methods have been used to control the temperature of processors. However, up-to-date microprocessors causes severe thermal problems, resulting in increased cooling cost. Therefore, recent studies have focused on architecture-level thermal-aware design techniques than mechanical cooling methods. Even though architecture-level thermal-aware design techniques are efficient for reducing the temperature of processors, they cause performance degradation inevitably. Therefore, if the mechanical cooling methods can manage the thermal problems of processors efficiently, the performance can be improved by reducing the performance degradation due to architecture-level thermal-aware design techniques such as dynamic thermal management. In this paper, we analyze the cooling efficiency of high-performance multicore processors according to mechanical cooling methods. According to our experiments using air cooler and liquid cooler, the liquid cooler consumes more power than the air cooler whereas it reduces the temperature more efficiently. Especially, the cost for reducing $1^{\circ}C$ is varied by the environments. Therefore, if the mechanical cooling methods can be used appropriately, the temperature of high-performance processors can be managed more efficiently.
Keywords
High-performance processor; Hotspot; Mechanical cooling method; Cooling cost; Cooling efficiency;
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Times Cited By KSCI : 3  (Citation Analysis)
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1 "Energy-Optimal Dynamic Thermal Management : Computation and Cooling Power-Optimization", Donghwa Shin, Sung Woo Chung, Eui-Young Chung, Naehyuk Chang, IEEE Trans. On Industrial Informatics, Vol. 6, No 3. Aug. 2010
2 Peltier Module, http://blog.daum.net/iantech/6045548
3 Peltier Module, http://blog.daum.net/iantech/6045548
4 HWMonitor, http://www.cpuid.com
5 A. K. Coskun, A. B. Kahng, T. S. Rosing, "Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures," In Proceedings of 12th Euromicro Conference on Digital System Design and Architectures, Methods and Tools, pp. 183-190, 2009.
6 K. Sankaranarayanan, S. Velusamy, M. Stan, and K. Skadron, "A Case for Thermal-Aware Floorplanning at the Microarchitectural Level," Journal of Instruction-Level Parallelism, vol. 7, pp. 1-16, July 2005.
7 D. Brooks and M. Martonosi, "Dynamic Thermal Management for High-Performance Microprocessors," In Proceedings of the 7th International Symposium on High-Performance Computer Architecture, pp. 172-182, Jan. 2001.
8 K. Choi, R. Soma, M. Pedram, "Dynamic voltage and frequency scaling based on workload decomposition," In Proceedings of the 2004 international symposium on Low power electronics and design, pp. 174-179, Aug. 2004.
9 L. Benini, G. De Micheli, E. Macii, M. Poncino, R. Scarsi, "Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers," In Transactions on Design Automation of Electronic Systems (TODAES), vol. 4, issue. 4, pp. 351-375, Oct. 1999.   DOI   ScienceOn
10 R. Mahajan, "Thermal Management of CPUs: A Perspective on Trends, Needs, and Opportunities," In the 8th International Workshop on THERMal INvestigations of ICs and Systems 2002.
11 P. Dadvar, K. Skadron, "Potential thermal security risks," In Proceedings of the IEEE/ASME Semiconductor Thermal Measurement, Modeling, and Management Symposium (SEMI-THERM), pp. 229-234, March 2005.
12 L. Yeh, R. Chy, "Thermal Management of Microelectronic Equipment," American Society of Mechanical Engineering, 2001.
13 Z. Zhijun, L. R. Hoover, and A. L. Phillips, "Advanced thermal architecture for cooling of high power electronics," Components and Packaging Technologies, IEEE Transactions on, vol. 25, no. 4, pp. 629-634, Dec. 2002.   DOI   ScienceOn
14 H.J. Choi, N.R. Yang, J.A. LEE, J.M. Kim, C.H. Kim, "Processor Design Technique for Low-Temperature Filter Cache," Journal of The Korea Society of Computer and Information, Vol. 15, No. 1, pp. 1-12, Jan. 2010.   DOI
15 S. Gunther, F. Binns, D. Carmean, and J. Hall. "Managing the Impact of Increasing Microprocessor Power Consumption," Intel Technology Journal, 5, Feb. 2001.
16 J.H. Jeong, "Heat-radiant and Cooling Device of Central Processing Unit and Peripheral devices," JOURNAL OF KOREA INTELLECTUAL PATENT SOCIETY, Vol 8, No. 4, pp. 33-43, Dec. 2006.
17 J.H. Choi, "Thermal Management for Multi-core Processor and Prototyping Thermal-aware Task Scheduler," Journal of KIISE : Computer Systems and Theory, vol.35, no.7-8, pp.354-360, Aug. 2008.
18 Y.J. Park, J.M. Kim, C.H. Kim, "Low-power Filter Cache Design Technique for Multicore Processors," Journal of The Korea Society of Computer and Information, Vol. 14, No. 12, pp. 9-16, Dec. 2009.
19 J.H. Kong, S.W. Chung, "Recent Thermal Management Techniques for Microprocessors," Communications of KIISE, Vol. 27, No. 11, pp. 72-79, Nov. 2009
20 F. Pollack. "New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies," International Symposium on Microarchitecture (MICRO-32) keynote speech, 1999.
21 N. P. Jouppi, "Improving Direct-Mapped Cache Perfor mance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," In Proceedings of 17th Annual International Symposium on Computer Architecture, pp. 364-373, June 1990.
22 M. Powell, S.H. Yang, B. Falsafi, K. Roy, and T.N. Vijaykumar, "Gated-Vdd : A circuit technique to reduce leakage in deep-submicron cache memories," In Proceedings of International Symposium on Low Power Electronics and Design, pp. 90-95, July 2000.
23 S. J. E. Wilson, N. P. Jouppi, "An enhanced access and cycle time model for on-chip caches," Technical Report 93/5, Digital Equipment Corporation, Western Research Laboratory, 1994.