• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.3 s.357
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• pp.61-67
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• 2007

In Reed Solomon decoder, when there are more than 4 error symbols, we usually use Chien search machine to find those error positions. In this case, classical method requires complex and relatively slow digital circuitry to implement it. In this paper we propose New fast and cost effective Chien search machine design method using Galois Subfield transformation. Example is given to show the method is working well. This new design can be applied to the case where there are more than 5 symbol errors in the Reed-Solomon code word.

• Journal of Sensor Science and Technology
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• v.24 no.3
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• pp.188-193
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• 2015

This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.5
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• pp.15-20
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• 2012

In this paper, we show new method to find the error locations of received Reed-Solomon code word. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square/$X^4$ calculating circuit, parallel processing and not using the very complex Divider. The Reed Solomon decoder using this new Chien Machine can be applicated for data protection of almost all digital communication and consumer electronic devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.170-178
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• 2004

In this work a high speed 8-error correcting Reed-Solomon decoder is designed using the modified Euclid algorithm. Decoding algorithm of Reed-Solomon codes consists of four steps, those are, compute syndromes, find error-location polynomials, decide error-locations, and determine error values. The decoding speed is increased and the latency is reduced by using the parallel architecture in the syndrome generator and a faster clock speed in the modified Euclid algorithm block. In addition. the error locator polynomial in Chien search block is separated into even and odd terms to increase the overall speed of the decoder. All the functionalities of the decoder are verified first through C++ programs. Verilog is used for hardware description, and then the decoder is synthesized with a $.25{\mu}m$ CMOS TML library. The functionalities of the chip is also verified through test vectors. The clock speed of the chip is 250MHz, and the maximum data rate is 1Gbps.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.262-265
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• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk provides double error detecting and correcting capability. The most complex circuit in the RS decoder is part for solving the error location numbers from error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and Performed logic synthesis using the SYNOPSYS CAD tool. Then, the RS decoder has been implemented with FPGA. The total umber of gate is about 11,000 gates and it operates at 20MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8A
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• pp.821-828
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• 2008

In this paper, we present an optimized design of RS(23,17) decoder for UWB, which uses the pipeline structured-modified Euclidean(PS-ME) algorithm. Firstly, the modified processing element(PE) block is presented in order to get rid of degree comparison circuits, registers and MUX at the final PE stage. Also, a degree computationless decoding algorithm is proposed, so that the hardware complexity of the decoder can be reduced and high-speed decoder can be implemented. Additionally, we optimize Chien search algorithm, Forney algorithm, and FIFO size for UWB specification. Using Verilog HDL, the proposed decoder is implemented and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 17,628.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.165.2-165
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• 2001

A number of previous researches in evolutionary algorithm are based on the study of facets we observe in natural evolution. The individuals of species in natural evolution occupy their own niche that is a subdivision of the habitat. This means that two species with the similar requirements cannot live together in the same niche. This is known as the competitive exclusion principle, i.e., complete competitors cannot coexist. In this paper, a new evolutionary programming algorithm adopting this concept is presented. Similarly in the case of natural evolution , the algorithm Includes the concept of niche obtained by partitioning a search space and the competitive exclusion principle performed by migrating individuals. Cell partition and individual migration strategies are used to preserve search diversity as well as to speed up convergence of an ...

• Industrial Engineering and Management Systems
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• v.12 no.4
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• pp.306-316
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• 2013

The semiconductor industry has grown rapidly, and subsequently production planning problems have raised many important research issues. The reentrant flow-shop (RFS) scheduling problem with time windows constraint for harddisk devices (HDD) manufacturing is one such problem of the expanded semiconductor industry. The RFS scheduling problem with the objective of minimizing the makespan of jobs is considered. Meeting this objective is directly related to maximizing the system throughput which is the most important of HDD industry requirements. Moreover, most manufacturing systems have to handle the quality of semiconductor material. The time windows constraint in the manufacturing system must then be considered. In this paper, we propose a hybrid genetic algorithm (HGA) for improving chromosomes/offspring by checking and repairing time window constraint and improving offspring by left-shift routines as a local search algorithm to solve effectively the RFS scheduling problem with time windows constraint. Numerical experiments on several problems show that the proposed HGA approach has higher search capability to improve quality of solutions.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.131-136
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MB-OFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MB-OFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.195-198
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MBOFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MBOFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.