• The KSFM Journal of Fluid Machinery
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• v.6 no.4 s.21
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• pp.21-28
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• 2003

CMP (Chemical Mechanical Polishing) is to achieve adequate local and global planarization for future sub-micrometer VLSI requirements. In designing CMP, numerical computation is quite helpful in terms of reducing the amount of experimental works. Stresses on pad, concentration of particles and particle tracking are studied for design. In this research, the optimization of grooved pad shape of CMP is performed through numerical investigation of slurry flow in CMP process. The result indicates that the combination of sinusoidal groove and skewed pad is the most optimal shape among the twenty candidates. Useful information can be obtained in velocity, pressure, stress, concentration of particles and particles trajectories, etc.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.622-625
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• 2004

The CMP monitoring system was newly developed by the aid of friction force measurement, resulting from installation of piezoelectric quartz sensor on R&D polisher. The correlation between friction and CMP results was investigated in terms of tribological aspects by using the monitoring system. Various friction signals were monitored and analyzed by the change of experimental conditions such as pressure, velocity, pad and slurry. First of all, the lubrication regimes were classified with Sommerfeld Number through measuring coefficient of friction in ILD CMP. And then, the removal mechanism of abrasives could be understood through the correlation with removal rate and coefficient of friction. Especially, the amount of material removal per unit sliding distance is directly proportional to the friction force. The uniformity of CMP performances was also deteriorated as coefficient of friction increased.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.35-38
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• 2000

In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.l8um semiconductor device. Through reverse moat pattern process, reduced moat density at high moat density, STI CMP process with low selectivity could be to fit polish uniformity between low moat density and high moat density. Because this reason, in-situ motor current end point detection method is not fit to the current EPD technology with the reverse moat pattern. But we use HSS without reverse moat pattern on STI CMP and take end point current sensing signal.[1] To analyze sensing signal and test extracted signal, we can to adjust wafer difference within $110{\AA}$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.14-17
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• 2000

The rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.18um semiconductor device. To employ in STI CMP, the reverse moat process has been added thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STi CMP was not equal hence the devices must to be effected, that is, the damage was occured in the device dimension in the case of excessive CMP process and the nitride film was remained on the device dimension in the case of insufficient CMP process than these defects affect the device characteristics. We studied the current sensing method in STI-CMP with the reverse moat pattern.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.64-64
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• 2003

고집적화된 시스템 LSI 반도체 소자 제조 공정에서 소자의 고속화 및 고성능화에 따른 배선층수의 증가와 배선 패턴 미세화에 대한 요구가 갈수록 높아져, 광역평탄화가 가능한 STI CMP(Shallow Trench Isolation Chemical-Mechanical-Polishing)공정의 중요성이 더해가고 있다. 이러한 STI CMP 공정에서 세리아 슬러리에 첨가되는 계면활성제의 농도에 따라 산화막과 질화막 사이의 연마 선택비를 제어하는 것이 필수적 과제로 등장하고 있다. 일반적인 CMP 공정에서 압력 증가에 따른 연마 제거량이 Prestonian 거동을 나타내는 반면, 연마 입자의 크기를 변화시켜 계면활성제의 농도를 달리 하였을 경우, 압력 변화에 따라 Non-Prestonian 거동이 나타나는 것을 고찰할 수 있었다. 따라서 본 연구에서는 세리아 슬러리 내에 첨가되는 계면활성 제의 농도와 연마입자의 크기를 달리한 후, 압력을 변화시킴으로 나타나는 non-Prestonian 거동에 미치는 영향에 대하여 연구하였다.

• Transactions on Electrical and Electronic Materials
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• v.6 no.5
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• pp.225-228
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• 2005

In this work, we studied the optimized copper thickness in Cu ECP (Electrochemical Plating). In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge (bump, hump or over-plating amount), Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness. In the aspect of bump and dishing, the bulge increased according as target plating thickness decreased. Dishing of edge was larger than center of wafer. Also in case of electrical property, metal line resistance distribution became broad gradually according as Cu ECP thickness decreased. In conclusion, at least $20\%$ reduced Cu ECP thickness from current baseline; $0.8\;{\mu}m$ and $1.0\;{\mu}m$ are suitable to be adopted as newly optimized Cu ECP thickness for local and intermediate layer.

• Proceedings of the KIEE Conference
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• 2006.07a
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• pp.605-606
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• 2006

CMP(chemical mechanical polishing) process has been attracted as an essential technology of multi-level interconnection. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, slurry dominates more than 40 %. So, we focused how to reduce the consumption of raw slurry. In this paper, $ZrO_2$,$CeO_2$, and $MnO_2$ abrasives were added de-ionized water (DIW) and pH control as a function of KOH contents. We have investigate the possibility of new abrasive for the oxide CMP application.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.2237-2238
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• 2006

CMP(chemical mechanical polishing) process has been attracted as an essential technology of multi-level interconnection. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, slurry dominates more than 40 %. So, we focused how to reduce the consumption of raw slurry. In this paper, $ZrO_2$, $CeO_2$, and $MnO_2$ abrasives were added de-ionized water (DIW) and pH control as a function of KOH contents. We have investigate the possibility of new abrasive for the oxide CMP application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.139-140
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• 2006

PZT박막은 비휘발성 재료로 유전율이 높고 항전력이 작으면서 잔류 분극랑이 크기 때문에 적합한 특성을 가지고 FeRAM에 매력적인 물질이다. CMP(chemical mechanical polishing)는 기존의 회생막의 전면 식각 공정과는 달리 특정 부위의 제거 속도를 조절함으로써 평탄화 하는 기술로 wafer 전면을 회전하는 탄성 패드 사이에 액상의 Slurry를 투입하여 연마하는 기술이다. 본 논문에서는 CMP 공정으로 제조한 PZT박막 캐패시터에서 CMP 후처리공정(세척)의 유무 및 종류에 따라 피로특성에 대하여 연구하였다, PZT 박막의 캐패시터의 피로 특성을 연구한 결과 CMP 후처리공정 SC-l용액을 사용하여 세정공정을 하였을때 가장 향상된 PZT 캐패시터의 피로특성이 나타났다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.368-369
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• 2006

Ferroelectric thin films have attracted much attention for applications in nonvolatile ferroelectric random access memories(NVFeRAM) from the view points of high speed operation, low power consumption, and large scale Integration[1,2]. Among the FRAM, BLT is of particular interest. as it is not only crystallized at relatively low processing temperature, but also shows highly fatigue resistance and large remanent polarization Meanwhile, these submicron ferroelectric capacitors were fabricated by a damascene process using Chemical mechanical polishing (CMP). BLT capacitors were practicable by a damascene process using CMP. The P-E hysteresis were measured under an applied bias of ${\pm}5V$ by using an RT66A measurement system. The electric properties such as I-V were determined by using HP4155A analysers.