• 제목/요약/키워드: Chemical mechanical planarization

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Copper CMP시 연마균일성에 관한 기계적 해석 (Mechanical Analysis on Uniformity in Copper Chemical Mechanical Planarization)

  • 정해도;이현섭;김형재
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.49-50
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    • 2006
  • The studies on Cu CMP have focused on material removal and its mechanisms. Although many studies have been conducted on the mechanism of Cu CMP, a study on uniformity in Cu CMP is still unknown. Since the aim of CMP is global and local planarization, the approach to uniformity in Cu CMP is essential to elucidate the Cu CMP mechanism as well. The main purpose of the experiment reported here was to investigate the roles of slurry components in the formation of the uniformity in Cu CMP. All the results of in this study showed that the uniformity in Cu CMP could be controlled by the contents of slurry components.

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산화막 CMP에서 패드 두께가 연마율과 연마 불균일도에 미치는 영향 (Effect of Pad Thickness on Removal Rate and Within Wafer Non-Uniformity in Oxide CMP)

  • 배재현;이현섭;박재홍;니시자와 히데키;키노시타 마사하루;정해도
    • 한국전기전자재료학회논문지
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    • 제23권5호
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    • pp.358-363
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    • 2010
  • The polishing pad is important element for polishing characteristic such as material removal rate(MRR) and within wafer non-uniformity(WIWNU) in the chemical mechanical planarization(CMP). The result of the viscoelasticity measurement shows that 1st elastic modulus is increased and 2nd elastic modulus is decreased when the top pad is thickened. The finite element analysis(FEA) was conducted to predict characteristic of polishing behavior according to the pad thickness. The result of polishing experiment was similar with the FEA, and it shows that the 1st elastic modulus affects instantaneous deformation of pad related to MRR. And the 2nd elastic modulus has an effect on WIWNU due to the viscoelasticity deformation of pad.

W-slurry의 산화제 첨가량에 따른 Cu-CMP특성 (The Cu-CMP's features regarding the additional volume of oxidizer to W-Slurry)

  • 이우선;최권우;서용진
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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    • pp.370-373
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    • 2003
  • As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical Planarization(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper depostion is a mature process from a historical point of view, but a very young process from a CMP persperspective. While copper electrodepostion has been used and stuidied for dacades, its application to Cu damascene wafer processing is only now ganing complete accptance in the semiconductor industry. The polishing mechanism of Cu CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper pasivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

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고유전율막의 CMP 특성 (Chemical Mechanical Polishing Characteristics of High-k Thin Film)

  • 박성우;서용진;이우선
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.55-56
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    • 2006
  • In this paper, we first applied the chemical mechanical polishing (CMP) process to the planarization of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. BST ($Ba_{0.6}Sr_{0.4}TiO_3$), PZT ($Pb_{1.1}(Zr_{0.52}TiO_{0.48})O_3$) and BTO ($BaTiO_3$) ferroelectric film are fabricated by the sol-gel method. And then, we compared the structural characteristics before and after CMP process of BST, PZT, BTO films. Their dependence on slurry composition was also investigated. We expect that our results will be useful promise of global planarization for ferroelectric random access memories (FRAM) application in the near future.

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구리 CMP 후 연마입자 제거에 화학 기계적 세정의 효과 (Effect of Chemical Mechanical Cleaning(CMC) on Particle Removal in Post-Cu CMP Cleaning)

  • 김영민;조한철;정해도
    • 대한기계학회논문집A
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    • 제33권10호
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    • pp.1023-1028
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    • 2009
  • Cleaning is required following CMP (chemical mechanical planarization) to remove particles. The minimization of particle residue is required with each successive technology generation, and the cleaning of wafers becomes more complicated. In copper damascene process for interconnection structure, it utilizes 2-step CMP consists of Cu and barrier CMP. Such a 2-steps CMP process leaves a lot of abrasive particles on the wafer surface, cleaning is required to remove abrasive particles. In this study, the chemical mechanical cleaning(CMC) is performed various conditions as a cleaning process. The CMC process combined mechanical cleaning by friction between a wafer and a pad and chemical cleaning by CMC solution consists of tetramethyl ammonium hydroxide (TMAH) / benzotriazole (BTA). This paper studies the removal of abrasive on the Cu wafer and the cleaning efficiency of CMC process.

전해액의 농도가 Cu 전극의 전기화학적 특성에 미치는 영향 (Effects of Concentration of Electrolytes on the Electrochemical Properties of Copper)

  • 이성일;박성우;한상준;이영균;서용진
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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    • pp.82-82
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    • 2007
  • The chemical mechanical polishing (CMP) process has been widely used to obtain global planarization of multilevel interconnection process for ultra large scale. integrated circuit applications. Especially, the application of copper CMP has become an integral part of several semiconductor device and materials manufacturers. However, the low-k materials at 65nm and below device structures because of fragile property, requires low down-pressure mechanical polishing for maintaining the structural integrity of under layer during their fabrication. In this paper, we studied electrochemical mechanical polishing (ECMP) as a new planarization technology that uses electrolyte chemistry instead of abrasive slurry for copper CMP process. The current-voltage (I-V) curves were employed we investigated that how this chemical affect the process of voltage induced material removal in ECMP of Copper. This work was supported by grant No. (R01-2006-000-11275-0) from the Basic Research Program of the Korea Science.

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Experimental and Numerical Analysis of A Novel Ceria Based Abrasive Slurry for Interlayer Dielectric Chemical Mechanical Planarization

  • Zhuanga, Yun;Borucki, Leonard;Philipossian, Ara;Dien, Eric;Ennahali, Mohamed;Michel, George;Laborie, Bernard;Zhuang, Yun;Keswani, Manish;Rosales-Yeomans, Daniel;Lee, Hyo-Sang;Philipossian, Ara
    • Transactions on Electrical and Electronic Materials
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    • 제8권2호
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    • pp.53-57
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    • 2007
  • In this study, a novel slurry containing ceria as the abrasive particles was analyzed in terms of its frictional, thermal and kinetic attributes for interlayer dielectric (ILD) CMP application. The novel slurry was used to polish 200-mm blanket ILD wafers on an $IC1000_{TM}$ K-groove pad with in-situ conditioning. Polishing pressures ranged from 1 to 5 PSI and the sliding velocity ranged from 0.5 to 1.5 m/s. Shear force and pad temperature were measured in real time during the polishing process. The frictional analysis indicated that boundary lubrication was the dominant tribological mechanism. The measured average pad leading edge temperature increased from 26.4 to $38.4\;^{\circ}C$ with the increase in polishing power. The ILD removal rate also increased with the polishing power, ranging from 400 to 4000 A/min. The ILD removal rate deviated from Prestonian behavior at the highest $p{\times}V$ polishing condition and exhibited a strong correlation with the measured average pad leading edge temperature. A modified two-step Langmuir-Hinshelwood kinetic model was used to simulate the ILD removal rate. In this model, transient flash heating temperature is assumed to dominate the chemical reaction temperature. The model successfully captured the variable removal rate behavior at the highest $p{\times}V$ polishing condition and indicates that the polishing process was mechanical limited in the low $p{\times}V$ polishing region and became chemically and mechanically balanced with increasing polishing power.

실리카 슬러리의 에이징 효과 및 산화막 CMP 특성 (Aging Effects of Silica Slurry and Oxide CMP Characteristics)

  • 이우선;고필주;이영식;서용진;홍광준
    • 한국전기전자재료학회논문지
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    • 제17권2호
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    • pp.138-143
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    • 2004
  • CMP (Chemical Mechanical Polishing) technology for global planarization of multilevel interconnection structure has been widely studied for the next generation devices. Among the consumables for CMP process, especially, slurry and their chemical compositions play a very important role in the removal rates and within-wafer non-uniformity (WIWNU) for global planarization ability of CMP process. However, CMP slurries contain abrasive particles exceeding 1 ${\mu}{\textrm}{m}$ size, which can cause micro-scratch on the wafer surface after CMP process. Such a large size particle in these slurries may be caused by particle agglomeration in slurry supply-line. In this work, to investigate the effects of agglomeration on the performance of oxide CMP slurry, we have studied an aging effect of silica slurry as a function of particle size distribution and aging time during one month. We Prepared and compared the self-developed silica slurry by adding of alumina powders. Also, we have investigated the oxide CMP characteristics. As an experimental result, we could be obtained the relatively stable slurry characteristics comparable to aging effect of original silica slurry. Consequently, we can expect the saving of high-cost slurry.

실리콘 트랜치 구조 형성용 유전체 평탄화 공정 (Dielectric Layer Planarization Process for Silicon Trench Structure)

  • 조일환;서동선
    • 전기전자학회논문지
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    • 제19권1호
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    • pp.41-44
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    • 2015
  • 소자의 집적화에 필수적인 소자 분리공정에서 화학약품의 오염 문제등을 발생시키는 화학적 기계연마기술(CMP) 공정을 사용하지 않고 벌크 finFET(fin field effect transistor) 의 트랜치 구조를 형성할 수 있는 공정에 대하여 제안하였다. 사진 감광막 도포시 발생하는 두께차이와 희생층으로 사용되는 실리콘 질화막을 사용하면 에칭 공정만을 사용하여 상대적으로 표면 위로 돌출된 부분의 실리콘 산화막 층을 에칭하는 것은 물론 finFET 의 채널로 사용되는 실리콘 트랜치 구조를 한번에 형성할 수 있는 특징을 갖는다. 본 연구에서는 AZ1512 사진 감광막을 사용하여 50 나노미터급 실리콘 트랜치 구조를 형성하는 공정을 수행하였으며 그 결과를 소개한다.