• 대한전자공학회논문지SD
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• 제40권7호
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• pp.532-541
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• 2003

메모리에서의 대부분의 전력은 프리디코더 라인, 워드 라인, 그리고 비트 라인 등과 같은 커패시턴스가 큰 라인들에서 소모된다. 이 라인들에서의 전력 소모를 줄이기 위하여 전하 재활용과 전하 공유를 사용한 세 가지 기법들이 제안되었다. 이 기법들은 전하 재활용 프리디코더(charge recycling predecoder, CRPD), 전하 재활용 워드 라인 디코더(charge recycling word line decoder, CRWD), 그리고 롬을 위한 전하 공유 비트 라인(charge sharing bit line, CSBL)이다. CRPD와 CRWD는 프리디코더 라인과 워드 라인의 전하를 재활용하여 소모 전력을 반으로 줄여주고, 전하 공유 기법을 사용하는 CSBL은 롬 비트라인의 스윙 전압을 낮춤으로써 소모 전력을 크게 줄여준다. CRPD, CRWD, 그리고 CSBL의 소모 전력은 기존의 82%, 72%, 그리고 64%이다. 제안된 세 가지 기법들을 사용하는 전하 재활용 전하 공유 롬(charge recycling and charge sharing ROM, CRCS-ROM)이 0.35㎛ CMOS공정으로 제작되었다. 제작된 8K×16비트 CRCS-ROM의 코어 크기는 0.51㎟이고 3.3V 전원과 100㎒ 동작 주파수에서 8.63㎽ 을 소모하였다.

• 대한전자공학회논문지SD
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• 제41권5호
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• pp.99-105
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• 2004

더미 비트라인을 이용한 공유 커패시터 전하공유 롬(shared-capacitor charge-sharing ROM SCCS-ROM)이 제안되었다. SCCS-ROM은 기존의 전하공유 롬(charge-sharing ROM, CS-ROM)의 전하공유 기법으로 비트라인의 스윙전압을 줄였다. CS-ROM에서는 출력 비트 마다 3개의 작은 커패시턴스들이 필요하지만, 제안된 SCCS-ROM은 그 커패시터들을 공유함으로써 필요한 커패시터의 수를 단지 3개로 줄였다. 또한, 더미 비트라인들(dummy bit lines)로 커패시터들을 구현함으로써, 잡음내성을 증가시켰을 뿐만 아니라 소모전력 또한 줄였다. 8K×15bi1s의 SCCS-ROM이 0.35㎛ CMOS 공정으로 구현되었다. SCCS-ROM은 3.3V의 100㎒ 동작에서 8.63㎽의 전력을 소모하였다. 시뮬레이션에서 SCCS-ROM은 CS-ROM보다 8.4% 적은 전력을 소모하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.549-556
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• 2014

This paper proposes a highly power-efficient single-inductor multiple-outputs (SIMO) DC-DC converter with a gate charge sharing method in which gate charges of output switches are shared to improve the power efficiency and to reduce the switching power loss. The proposed converter was fabricated by using a $0.18{\mu}m$ CMOS process technology with high voltage devices of 5 V. The input voltage range of the converter is from 2.8 V to 4.2 V, which is based on a single cell lithium-ion battery, and the output voltages are 1.0 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V. Using the proposed gate charge sharing method, the maximum power efficiency is measured to be 87.2% at the total output current of 450 mA. The measured power efficiency improved by 2.1% compared with that of the SIMO DC-DC converter without the proposed gate charge sharing method.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.161-165
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• 2023

This paper designed a voltage feedback driving circuit to compensate for the characteristic deviation of the Active Matrix Organic Light Emitting Diode driving Thin Film Transistor. This paper describes a stable and fast circuit by applying charge sharing and polar stabilization methods. A 12-inch Organic Light Emitting Diode with a Double Wide Ultra eXtended Graphics Array resolution creates a screen distortion problem for line parasitism, and charge sharing and polar stabilization structures were applied to solve the problem. By applying Charge Sharing, all data lines are shorted at the same time and quickly positioned as the average voltage to advance the compensated change time of the gate voltage in the next operation period. A buffer circuit and a current pass circuit were added to lower the Amplifier resistance connected to the line as a polar stabilization method. The advantage of suppressing the Ringing of the driving Thin Film Transistor can be obtained by increasing the stability. As a result, a circuit was designed to supply a stable current to the Organic Light Emitting Diode even if the characteristic deviation of the driving Thin Film Transistor occurs.

• 대한전자공학회논문지SD
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• 제44권1호
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• pp.76-83
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• 2007

본 논문에서는 한 개의 전하공유 커패시터와 계층적 비트라인을 이용한 저전력 롬을 제안하였다. (single charge-sharing capacitor ROM: SCSC-ROM) 제안된 SCSC-ROM은 전하공유 커패시터와 계층적 비트라인으로 비트라인의 전력소모를 크게 줄였다. 한 개의 전하공유 커패시터를 이용한 전하공유 기법으로 비트라인의 swing 전압을 크게 낮춤으로써 비트라인에서의 전력소모를 줄였다. 이때, 전하공유 커패시터를 dummy 비트라인으로 구현하여 노이즈에 강할 뿐만 아니라 설계를 쉽게 하였다. 계층적 비트라인 기법으로 비트라인의 커패시턴스를 줄임으로써 전력소모를 더욱 줄였다. 또한, 계층적 워드라인 디코더를 제안하여 컨트롤과 프리디코더에서 소모되는 전력을 줄일 수 있었다. 시뮬레이션 결과에서 $4K{\times}32$비트의 SCSC-ROM의 소모전력은 기존의 롬의 37%로 줄었다. 칩은 $0.25{\mu}m$ CMOS 공정으로 제작되었고, 2.5V의 240MHz 동작에서 8.2mW를 소모하였다.

• 센서학회지
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• 제14권1호
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• pp.28-32
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• 2005

In this paper, a CMOS integrated detection circuit for capacitive type fingerprint sensor signal processing is described. We designed a detection circuit of charge-sharing sensing scheme. The proposed detection circuit increases the voltage difference between a ridge and valley. The test chip is composed of $160{\times}192$ array sensing cells (12 by $12.7{\;}mm^{2}$). The chip was fabricated on a 0.35 m standard CMOS process. Measured difference voltage between a ridge and valley was 0.95 V.

• 전자공학회논문지A
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• 제31A권8호
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• pp.34-45
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• 1994

We studied threshold voltages and I-V characteristics. considering short channel effect of the fully depleted thin film n-channel SOI MOSFET. We presented a charge sharing model when the back surface of short channel shows accumulation depletion and inversion state respectively. A degree of charge sharing can be compared according to each of back-surface conditions. Mobility is not assumed as constant and besides bulk mobility both the mobility defined by acoustic phonon scattering and the mobility by surface roughness scattering are taken into consideration. I-V characteristics is then implemented by the mobility including vertical and parallel electric field. kThe validity of the model is proved with the 2-dimensional device simulation (MEDICI) and experimental results. The threshold voltage and charge sharing region controlled by source or drain reduced with increasing back gate voltage. The mobility is dependent upon scattering effect and electric field. so it has a strong influence on I-V characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.331-338
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• 2014

A charge-pump circuit using a current-bypass technique, which suppresses charge sharing and reduces the sub-threshold currents, helps to decrease phase-locked loop (PLL) jitter without resorting to a feedback amplifier. The PLL shows no stability issues and no power-up problems, which may occur when a feedback amplifier is used. The PLL is implemented in 0.11-${\mu}m$ CMOS technology to achieve 0.856-ps RMS and 8.75-ps peak-to-peak jitter, which is almost independent of ambient temperature while consuming 4 mW from a 1.2-V supply.

• Journal of information and communication convergence engineering
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• 제6권1호
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• pp.43-46
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• 2008

This paper proposes an advanced test circuit for detecting the connectivity between a drum ring of laser printer and PCB. The detection circuit of charge sharing is proposed, which minimizes the influences of internal parasitic capacitances. The test circuit is composed of precharge circuit, analog comparator, level shifter. Its functional operation is verified using $0.6{\mu}m$ 3.3V/40V CMOS process parameter by HSPICE. Access time is100ns. Layout of the drum contact test circuit is $465{\mu}m\;{\times}\;117{\mu}m$.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제49권4호
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• pp.282-290
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• 2000

In this paper, the charge control with the input voltage feedback is proposed for the input series-output series-output parallel connected converter configuration for the high speed train power system application. This control scheme accomplishes the output current sharing for the output-parallel connected modules as well as the input voltage sharing for the input series connected modules for all operating conditions including the transients. It also offers the robustness for the input voltage sharing control according to the component value mismatches among the modules. And this configuration enables the usage of MOSFET for a high voltage system allowing a higher switching frequency for lighter system weight and smaller size. The performance of the proposed scheme is verified through the experimental results.