• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.136-136
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• 2011

반도체 및 전자기기 산업에 있어서 NVM은 아주 중요한 부분을 차지하고 있다. NVM은 디스플레이 분야에 많은 기여를 하고 있는데, 측히 AMOLED에 적용이 가능하여 온도에 따라 변하는 구동 전류, 휘도, color balance에 따른 문제를 해결하는데 큰 역할을 한다. 본 연구에서는 bottom gate 구조의 nc-Si NVM 실험을 진행하였다. P-type silicon substrate (0.01~0.02 ${\Omega}-cm$) 위에 Blocking layer 층인 SiO2 (SiH4:N2O=6:30)를 12.5nm증착하였고, Charge trap layer 층인 SiNx (SiH4:NH3=6:4)를 20 nm 증착하였다. 마지막으로 Tunneling layer 층인 SiOxNy은 N2O (2.5 sccm) 플라즈마 처리를 통해 2.5 nm 증착하였다. 이러한 ONO 구조층 위에 nc-Si을 50 nm 증착후에 Source와 Drain 층을 Al 120 nm로 evaporator 이용하여 증착하였다. 제작한 샘플을 전기적 특성인 Threshold voltage, Subthreshold swing, Field effect mobility, ON/OFF current ratio, Programming & Erasing 특성, Charge retention 특성 등을 알아보았다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.339-339
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• 2012

현재 MOS 소자에 사용되고 있는 $SiO_2$ 산화막은 그 두께가 얇아짐에 따라 Gate Leakage current와 여러 가지 신뢰성 문제가 대두되고 있고, 이를 극복하고자 High-k물질을 사용하여 기존에 발생했던 Gate Leakage current와 신뢰성 문제를 해결하고자 하고 있다. 본 실험에서는 High-k(hafnium) Gate Material에 온도 변화를 주었을 때 여러 가지 전기적인 특성 변화를 보는 방향으로 연구를 진행하였다. 기본적인 P-Type Si기판을 가지고, 그 위에 있는 자연적으로 형성된 산화막을 제거한 후 Hafnium Gate Oxide를 Atomic Layer Deposition (ALD)를 이용하여 증착하고, Aluminium을 전극으로 하는 MOS-Cap 구조를 제작한 후 FGA 공정을 진행하였다. 마지막으로 $300^{\circ}C$, $450^{\circ}C$로 30분정도씩 Annealing을 하여, 온도 조건이 다른 3가지 종류의 샘플을 준비하였다. 3가지 샘플에 대해서 각각 I-V (Gate Leakage Current), C-V (Mobile Charge), Interface State Density를 분석하였다. 그 결과 Annealing 온도가 올라가면 Leakage Current와 Dit(Interface State Density)는 감소하고, Mobile Charge가 증가하는 것을 확인할 수가 있었다. 본 연구는 향후 High-k 물질에 대한 공정 과정에서의 다양한 열처리에 따른 전기적 특성의 변화 대한 정보를 제시하여, 향후 공정 과정의 열처리에 대한 방향을 잡는데 도움이 될 것이라 판단된다.

• Journal of the Korean Ceramic Society
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• v.49 no.6
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• pp.631-636
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• 2012

Conventional SONOS (poly-silicon/oxide/nitride/oxide/silicon) type memory is associated with a retention issue due to the continuous demand for scaled-down devices. In this study, $Al_2O_3/Y_2O_3/SiO_2$ (AYO) multilayer structures using a high-k $Y_2O_3$ film as a charge-trapping layer were fabricated for nonvolatile memory applications. This work focused on improving the retention properties using a $Y_2O_3$ layer with different tunnel oxide thickness ranging from 3 nm to 5 nm created by metal organic chemical vapor deposition (MOCVD). The electrical properties and reliabilities of each specimen were evaluated. The results showed that the $Y_2O_3$ with 4 nm $SiO_2$ tunnel oxide layer had the largest memory window of 1.29 V. In addition, all specimens exhibited stable endurance characteristics (program/erasecycles up to $10^4$) due to the superior charge-trapping characteristics of $Y_2O_3$. We expect that these high-k $Y_2O_3$ films can be candidates to replace $Si_3N_4$ films as the charge-trapping layer in SONOS-type flash memory devices.

• Journal of Applied Reliability
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• v.10 no.1
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• pp.65-71
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• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.12
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• pp.792-796
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• 2014

In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond $0.18{\mu}m$ CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2000.11a
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• pp.36-39
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• 2000

A small electrical potential difference which appears on any solid body when subjected to illumination by a modulated light beam generated by laser is called photocharge voltage(PCV)[1,2]. This voltage is proportional to the induced change in the surface electrical charge and is capacitatively measured on various materials such as conductors, semiconductors, ceramics, dielectrics and biological objects. The amplitude of the detected signal depends on the type of material under investigation, and on the surface properties of the sample. In photocharge voltage spectroscopy measurements[3], the sample is illuminated by both a steady state monochromatic bias light and the pulsed laser. The monochromatic light is used to created a variation in the steady state population of trap levels in the surface and space charge region of semiconductor samples which does result in a change in the measured voltage. Using this technique the spatial variation of PCV can be utilized to evalulate the surface conditions of the sample and the variation of the PCV due to the monochromatic bias light are utilized to charactrize the surface states. A qualitative analysis of the proposed measuremen is present along with experimental results performed on amorphous silicon samples. The deposition temperature was varied in order to obtain samples with different structural, optical and electronic properties and measurements are related to the defect density in amorphous thin film.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.37-40
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• 1999

For the first time, charge trapping nonvolatile semiconductor memories with the deoxidized oxynitride gate dielectric is proposed and demonstrated. Gate dielectric wit thickness of less than 1 nm have been grown by postnitridation of pregrown thermal silicon oxides in NO ambient and then reoxidation. The nitrogen distribution and chemical state due to NO anneal/reoxidation were investigated by M-SIMS, TOF-SIMS, AES depth profiles. When the NO anneal oxynitride film was reoxidized on the nitride film, the nitrogen at initial oxide interface not only moved toward initial oxide interface, but also diffused through the newly formed tunnel oxide by exchange for oxygen. The results of reoxidized oxynitride(ONO) film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/N-rich SiON interface/Si-rich SiON(nitrogen diffused tunnel oxide)/Si substrate. In addition, the SiON and the S1$_2$NO Phase is distributed mainly near the tunnel oxide, and SiN phase is distributed mainly at tunnel oxide/Si substrate interface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.36-39
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• 2000

A small electrical potential difference which appears on any solid body when subjected to illumination by a modulated light beam generated by laser is called photocharge voltage(PCV)[1,2]. This voltage is proportional to the induced change in the surface electrical charge and is capacitatively measured on various materials such as conductors, semiconductors, ceramics, dielectrics and biological objects. The amplitude of the detected signal depends on the type of material under investigation, and on the surface properties of the sample. In photocharge voltage spectroscopy measurements[3], the sample is illuminated by both a steady state monochromatic bias light and the pulsed laser. The monochromatic light is used to created a variation in the steady state population of trap levels in the surface and space charge region of semiconductor samples which does result in a change in the measured voltage. Using this technique the spatial variation of PCV can be utilized to evaluate the surface conditions of the sample and the variation of the PCV due to the monochromatic bias light are utilized to characterize the surface states. A qualitative analysis of the proposed measurement is present along with experimental results performed on amorphous silicon samples. The deposition temperature was varied in order to obtain samples with different structural, optical and electronic properties and measurements are related to the defect density in amorphous thin film.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.53-53
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• 2009

Charge trap flash memory devices with modified tunneling barriers were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were used as engineered tunneling barriers. The VARIOT type tunneling barrier composed of oxide-nitride-oxide (ONO) layers revealed reliable electrical characteristics; long retention time and superior endurance. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase of interface state density at tunneling barrier/silicon channel by programming and erasing (P/E) stress.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.340-341
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• 2012

In this work, we investigated the effects of temperature stress on flatband voltage (VFB) shifts of HfO2-SiO2 double gate dielectrics devices. Fig. 1 shows a high frequency C-V of the device when a positive bias for 10 min and a subsequent negative bias for 10 min were applied at room temperature (300 K). Fig. 2 shows the corresponding plot when the same positive and negative biases were applied at a higher temperature (473.15 K). These measurements are based on the BTS (bias temperature stress) about mobile charge in the gate oxides. These results indicate that the positive bias stress makes no difference, whereas the negative bias stress produces a significant difference; that is, the VFB value increased from ${\Delta}0.51$ V (300 K, Fig. 1) to ${\Delta}14.45$ V (473.15 K, Fig. 2). To explain these differences, we propose a mechanism on the basis of oxygen vacancy in HfO2. It is well-known that the oxygen vacancy in the p-type MOS-Cap is located within 1 eV below the bottom of the HfO2 conduction band (Fig. 3). In addition, this oxygen vacancy can easily trap the electron. When heated at 473.15 K, the electron is excited to a higher energy level from the original level (Fig. 4). As a result, the electron has sufficient energy to readily cross over the oxide barrier. The probability of trap about oxygen vacancy becomes very higher at 473.15 K, and therefore the VFB shift value becomes considerably larger.