• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.9
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• pp.15-22
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• 2013

A new LED lamp driving technology with a charge pump instead of a conventional DC-DC converter is proposed. The proposed driving technology is used to control the LED lamp with digital dimming. The power loss in the zener diodes is reduced because the charging process of the capacitors is selectively controlled according to the digital control signal. From the experimental results, when dimming four LED lamps simultaneously, the average driving circuit efficiency of 89% is obtained, regardless of the dimming level. White light with color temperature over a range of 2800~7200K was produced by dimming control of red, green, blue and amber LED lamps with the proposed driving circuit. The characteristics of the driving circuits can be changed depending on the characteristics of the R, G, B, and A LED lamps. The efficiency of the driving circuits up to a maximum 89% can also be obtained depending on the combination of LED lamps. The driving technology with digital dimming control for LED lamps proposed in this paper would be effective for obtaining high efficiency in LED driving circuits and remote control of LED lamps using digital communications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.949-954
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• 2007

In this work, temperature stable frequency-to-voltage converter is proposed. In FVC circuit input frequency is converted into output voltage signal. A FLL is similar to PLL in the way that it generates an output signal which tracks an input reference signal. A PLL is built on a phase detector, a charge pump, and a low pass filter. However, FLL does not require the use of the phase detector, the charge pump and low pass filter. The FVC is designed by using $0.25{\mu}m$ CMOS process technology. From simulation results, the variation of output voltage is less than ${\pm}2%$ in the temperature range $0^{\circ}C\;to\;75^{\circ}C$ when the input frequency is from 70MHz to 140MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.675-677
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• 2009

통신기기에서 중요한 기술 중 하나인 PLL(Phase Locked Loop) 회로는 주기적인 신호를 원하는 대로, 정확한 고정점으로 잡아주는데 그 목적을 둔다. 일반적인 구조로 위상주파수검출기(Phase Frequency detector), 루프필터(Loop filter), 전압제어발진기(Voltage Controlled Oscillator), 디바이더(Divider)로 구성되어진다. 그러나 일반적인 PLL 구조로는 지터(jitter)가 증가하고 트랙(tracking) 속도가 느리다는 단점이 있다. 이를 보완하기 위해 루프필터 전단에 차지펌프(Charge pump) 회로를 추가하여 사용하고 있다. 본 논문에서는 CMOS를 이용한 PLL용 차지펌프를 설계하였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정 기술을 사용하여 CADENCE사의 Specter로 시뮬레이션 하였으며, Virtuso2로 레이아웃 하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.690-692
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• 2009

PLL은 위상주파수검출기(PFD), 차지펌프(Charge Pump), 루프필터(Loop Filter), 전압제어발진기(VCO), Divider로 구성하고 있는데 본 논문에서는 설계된 차지펌프 PLL을 시뮬레이션을 해보고 그 결과를 정리하고 레이아웃(layout)까지 하였다. 차지펌프 설계에 있어서 전류 부정합, 전하 공유, 전하주입, 누설 전류등을 고려할 필요가 있다. 설계된 차지펌프는 전류 부정합을 감소시키기 위해 전류뺄셈회로를 이용하여 전류 부정합을 감소시켰으며, spurs를 억제할 수 있도록 설계되였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정 기술을 사용하여 CADENCE사의 specter로 시뮬레이션 하였으며, virtuso2로 레이아웃 하였다.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2795-2797
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• 1999

Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both voltage-fed and current-fed electronic ballast. The proposed PFC circuits use valley-fill(VF) type DC-link stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant capacitors. In current-fed type, the charge pump capacitors are connected with the additional secondary-side of the power transformer. The measured PF and THD are higher than 0.99 and 15% for all proposed PFC circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.421-423
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• 2005

A bootstrap circuit for floating power supply has the advantage of being simple and inexpensive. However, the duty cycle and on-time are limited by the requirement to refresh the charge in the bootstrap capacitor. Hence, this paper deals with a design of charge pump circuit for a floating gate power supply of an IPM. The operation of the proposed circuit applied by three-phase inverter system for driving induction motor are verified through the experiments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2366-2373
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• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.21 no.8
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• pp.425-432
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• 2009

In this study, the improvement of cooling capacity by applying gas injection technique in a two-stage heat pump using R410A was experimentally investigated. A twin rotary type compressor with gas injection was applied to the heat pump system. The optimum refrigerant charge for the injection and the non-injection cycles was selected to achieve the maximum COP at the cooling standard condition. The injection cycle showed less optimum refrigerant charge than that of the non-injection cycle. The cooling performances of the injection and the non-injection cycles were measured and compared by varying compressor frequency from 40 to 90 Hz. The cooling capacity of the gas injection cycle was 1.6% -11.3% higher than that of the non-injection cycle. The COP of the gas injection cycle was 13.7% to 28.9% higher than that of the non-injection cycle at the same cooling capacity. The heat pump system showed stable operation after 30% of the injection valve opening.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.23 no.4
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• pp.273-280
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• 2011

In this study, the steady state performance of a $CO_2$ heat pump water heater was measured with a variation of operating conditions such as refrigerant charge amount, compressor frequency, EEV opening, and water mass flow rate. Transient state performance tests were also conducted to investigate major system effects associated with the interaction between the $CO_2$ heat pump water heater and the water tank. Optimum refrigerant charge amount for the system was 1600 g. At compressor frequencies of 50 Hz and 60 Hz, water mass flow rates of 95 kg/h and 105 kg/h, and EEV opening of 8% and 16%, the water heating temperatures were $65^{\circ}C$ and $68^{\circ}C$ and COPs were 3.0 and 2.8, respectively. In the transient condition, the instantaneous COP decreased with an increase in the inlet water temperature.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.82-87
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• 2008

This paper presents a new fast locking dual-slope phase-locked loop. The conventional dual-slope phase-locked loop consists of two charge pumps and two phase-frequency detectors. In this paper, the dual-slope phase-locked loop was achieved with a charge pump and a phase-frequency detector as adjusting a current of the charge pump according to the phase difference. The proposed circuit was verified by HSPICE simulation with a $0.35{\mu}m$ CMOS standard process parameter. The phase locking time of the proposed dual-slope phase-locked loop was $2.2{\mu}s$ and that of the single-slope phase-locke loop was $7{\mu}s$.