• 설비공학논문집
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• 제17권9호
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• pp.839-848
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• 2005

Plastic plate heat exchangers have many advantages over the conventional heat exchangers such as aluminum plate heat exchangers, rotary wheel heat exchangers and heat pipe heat exchangers which have been used for ventilation heat recovery in the air-conditioning systems. In the present study, pressure drop and heat transfer characteristics of plastic plate heat exchangers are investigated for various design parameters and operating conditions which affect the performance of the plastic plate heat exchangers. In flat plate type heat exchanger, material thickness and channel height of heat exchanger are considered, and corrugate size and heat transfer area are considered in case of corrugate type heat exchanger. Pressure drop and effectiveness of the corrugate type heat exchanger increase as the corrugate size decreases.

• Corrosion Science and Technology
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• 제15권5호
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• pp.245-252
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• 2016

The pipelines and equipments are degraded by flow-accelerated corrosion (FAC), and a large-scale test facility was constructed for simulate the FAC phenomena in secondary coolant environment of PWR type nuclear power plants. Using this facility, FAC test was performed on weld pipe (carbon steel and low alloy steel) at the conditions of high velocity flow (> 10 m/s). Wall thickness was measured by high temperature ultrasonic monitoring systems (four-channel buffer rod type and waveguide type) during test period and room temperature manual ultrasonic method before and after test period. This work deals with the complex effects of flow velocity on the wall thinning in weld pipe and the test results showed that the higher flow velocity induced different increasement of wall thinning rate for the carbon steel and low alloy steel pipe.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2009년도 춘계학술대회 논문집
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• pp.421-424
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• 2009

Superplastic deformation behavior and texture evolution after equal channel angular pressing (ECAP) of Zn-0.3Al alloy were investigated in this study. ECAP was conducted at temperatures from $40^{\circ}C$ to $160^{\circ}C$ on the plate type specimens of 5 mm thickness and 20 mm width. The specimens obtained by ECAP showed typical texture with basal poles tilted away from the ND toward ED. A series of compression and tensile tests was carried out at temperatures from RT to $200^{\circ}C$ under the strain rate from 0.03 to 10/s. After ECAP of the Zn-Al alloy, elongation was dramatically increased up to 1000% at above $60^{\circ}C$. The effects of ECAP on the texture and anisotropy in the superplastic deformation bebavior were found to be negligible.

• 대한기계학회논문집
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• 제12권1호
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• pp.116-122
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• 1988

본 연구에서는 공기와 물을 매질로 사용하여 3차원 계면파가 존재하는 근사수평 반류성층유동에서의 계면전단응력과 마찰계수를 결정하였다. 기상과 액상의 유량조건에 따라 3차원 계면파의 특성을 needle contact법에 의하여 측정 하였으며, 기상의 압력강하와 속도분포를 구하여 계면전단응력을 구하였다. 또 공학적인 응용을 위하여 3차원과 영역에서의 계면마찰계수에 관한 실험식을 개발하였다. 그리고 거칠은 고체표면에서의 마찰계수를 표현한 Nikuradse식을 이용하여 계면의 등가조도(equivalent roughness)를 계산하였으며 이것을 계면의 파고교란강도와 비교분석하여 계면전단응력에 영향을 미치는 인자들을 규명하였다.

• 대한조선학회논문집
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• 제43권2호
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• pp.268-274
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• 2006

Analysis has been made of the anti-corrosive property of organic coating under the shear stress of the flow by means of AC impedance method. Marine anti-corrosive painted panels were placed in the water channel with varying flow rate, thereby experiencing varying flow shear stress on the surfaces. The velocities of the salt water were ranged from 1.48 to 5.2 m/s and the coating thickness of from $70{\mu}m\;to\;140{\mu}m$. For all coating thicknesses investigated, the poorer anti-corrosive property and the lower adhesion strength have been found for the higher shear stress. It has been found that the shear stress accelerates the aging of organic marine coatings.

• ETRI Journal
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• 제19권4호
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• pp.402-413
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• 1997

A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권2호
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• pp.88-92
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• 2006

We present a microfluidic system with microvalves and a micropump that are easily integrated on the same substrate using the same fabrication process. The fabricated microfluidic system is suitable for use as a disposable device and its characteristics are optimized for use as a micro chemical analysis system (micro-TAS) and lab-on-a-chip. The system is realized by means of a polydimethylsiloxane (PDMS)-glass chip and an indium tin oxide (ITO) heater. We demonstrate the integration of the micropump and microvalves using a new thermopneumatic-actuated PDMS-based microfluidic system. A maximum pumping rate of about 730 nl/min is observed at. a duty ratio of 1 $\%$ and a frequency of 2 Hz with a fixed power of 500 mW. The measured power at flow cut-off is 500 mW for the microvalve whose channel width, depth and membrane thickness were 400 $\mu$m, 110 $\mu$m, and 320 $\mu$m, respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.275-277
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• 1999

A application possibility of photoresist flexible film for optical waveguide is proposed and described. The optical waveguide dimensions that is consists of Mach-zehnder interferometric and single channel waveguide based on the single-mode conditions in LiNbO$_3$ device was utilized and fabricated by wet etching technique. This Polymer material for core layer is SU-8/5O(Microchem.) and its refractive index from prism couping method was measured about 1.59 thickness about 10${\mu}{\textrm}{m}$ at wavelength 0.6328${\mu}{\textrm}{m}$. From the results, this work can show the possibility of fabricating a flexible optical waveguide in the field of integrated optics.

• 한국전기전자재료학회논문지
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• 제13권10호
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.