• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.105-105
• /
• 2012

We have developed a photoemission-assisted plasma-enhanced chemical vapor deposition (PAPE-CVD) [1,2], in which photoelectrons emitting from the substrate surface irradiated with UV light ($h{\nu}$=7.2 eV) from a Xe excimer lamp are utilized as a trigger for generating DC discharge plasma as depicted in Fig. 1. As a result, photoemission-assisted plasma can appear just above the substrate surface with a limited interval between the substrate and the electrode (~10 mm), enabling us to suppress effectively the unintended deposition of soot on the chamber walls, to increase the deposition rate, and to decrease drastically the electric power consumption. In case of the deposition of DLC gate insulator films for the top-gate graphene channel FET, plasma discharge power is reduced down to as low as 0.01W, giving rise to decrease significantly the plasma-induced damage on the graphene channel [3]. In addition, DLC thickness can be precisely controlled in an atomic scale and dielectric constant is also changed from low ${\kappa}$ for the passivation layer to high ${\kappa}$ for the gate insulator. On the other hand, negative electron affinity (NEA) of a hydrogen-terminated diamond surface is attractive and of practical importance for PAPECVD, because the diamond surface under PAPE-CVD with H2-diluted (about 1%) CH4 gas is exposed to a lot of hydrogen radicals and therefore can perform as a high-efficiency electron emitter due to NEA. In fact, we observed a large change of discharge current between with and without hydrogen termination. It is noted that photoelectrons are emitted from the SiO2 (350 nm)/Si interface with 7.2-eV UV light, making it possible to grow few-layer graphene on the thick SiO2 surface with no transition layer of amorphous carbon by means of PAPE-CVD without any metal catalyst.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.05a
• /
• pp.683-685
• /
• 2012

This paper have presented the analysis of the change for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET with two gates to be next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold chatacteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering is changed, and the deviation rate is changed for device parameters for DGMOSFET.

• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.35T no.2
• /
• pp.6-12
• /
• 1998

Thin film SOI(Silicon-on-insulator) device offer unique advantages such as reduction in short channel effects, improvement of subthreshold slope, higher mobility, latch-up free nature, and so on. But these devices exhibit floating-body effet such as current kink which inhibits the proper device operation. In this paper, the SOI NMOSFET with a T-type gate structure is proposed to solve the above problem. To simulate the proposed device with TSUPREM-4, the part of gate oxide was considered to be 30nm thicker than the normal gate oxide. The I-V characteristics were simulated with 2D MEDICI. Since part of gate oxide has different oxide thickness, the gate electric field strength is not same throughout the gate and hence the impact ionization current is reduced. The current kink effect will be reduced as the impact ionization current drop. The reduction of current kink effect for the proposed device structure were shown using MEDICI by the simulation of impact ionization current, I-V characteristics, and hole current distribution.

• Journal of the Korean Society of Safety
• /
• v.32 no.6
• /
• pp.61-67
• /
• 2017

Suspended sediment transport plays principal roles in morphological process of natural coastals. It is needed to understand the reason why interaction characteristics of solitary wave and suspended sediment. The present study shows that suspended sediment pickup derived on solitary wave celerity. The 2D prismatic open channel length is 12 m, width is 0.8 m, height is 0.75 m and slope is 1/6. Generation of solitary wave is used by rapidly opening the sluice gate. Bottom surface sediments are laid movable slope section by 0.03 m thickness and experimental sediments are used anathracite and jumoonjin sand. Techniques of suspended sediment pickup rate are designed equipment ASC(Absorptive Suspended sediment Collector). It could directly absorb 5 points suspended sediment by channel water depth. Solitary wave celerity is measued by ADV(Acoustic Doppler Velocimeter). Mounted two video cameras(Model No. : Sony, HDR-XR550) are used to image processing of suspended sediment concentration and turbidity. Suspended sediment pikcup rate(Einstein, 1950) is analyzed to nondimensionalization based on solitary wave celerity. The suspended sediment pickup rate is suggested that more effective plunging breaking type than spilling. The results indicates fundamental suspended sediment transport mechanism between solitary wave celerity and suspended sediment pickup based on laboratory experiments. Finally, the present study suggests that suspended sediment pickup rate by solitary wave is used only characteristics of sediment and solitary wave celerity.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.33 no.12
• /
• pp.109-116
• /
• 2005

Elastic-plastic structural analysis for regenerative cooling chamber of liquid rocket thrust chamber is performed. Uniaxial tension test is also conducted for the copper alloy in order to get material data necessary for the structure analysis. The results of uniaxial tension test reveal that copper alloy become ductile after brazing process and flow stress becomes lower as temperature becomes higher. As a result of structural analysis using the material data, the deformation of cooling channel is more increased by thermal load than by internal pressure of cooling fluid. Therefore, the results of analysis show that structural stability and cooling performance of combustion thrust chamber which is designed to endure mechanical load and minimized a channel thickness are improved by decreased thermal load as possible.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.11
• /
• pp.18-26
• /
• 1999

Recently, various simplified simulation techniques such as firite-difference beam propagation method and non-orthogonal coupled-mode theory have proposed to analyze the optical characteristics of tapered directional couplers supported by the coupling of two propagating modes. Although these approaches are often in sufficiently accurate, they do not provide the detailed solutions encountered in the analysis of tapered guiding structures. For this purpose, we introduce and utilize a newly developed modal transmission-line theory to analyze rigorously power transfer of the directional coupler. The numerical result reveals that the propagation constants of even and odd modes converge to a single value as increasing the spacer thickness between two symmetric tapered guides. Furthermore, 97% of the power incident into a guiding channel is transmitted to the other channel at the tapered angle ${\theta}=0.1^{\circ}$, and the efficiency of power transfer decreases dramatically as increasing the angle.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.6
• /
• pp.1-7
• /
• 2004

We performed two-dimensional (20) computer-based modeling and simulation of FinFET by solving the coupled Poisson-Schrodinger equations quantum-mechanically in a self-consistent manner. The simulation results are carefully investigated for FinFET with gate length(Lg) varying from 10 to 80nm and with a Si-fin thickness($T_{fin}$) varying from 10 to 40nm. Current-voltage (I-V) characteristics are compared with the experimental data. Device optimization has been performed in order to suppress the short-channel effects (SCEs) including the sub-threshold swing, threshold voltage roll-off, drain induced barrier lowering (DIBL). The quantum-mechanical simulation is compared with the classical appmach in order to understand the influence of the electron confinement effect. Simulation results indicated that the FinFET is a promising structure to suppress the SCEs and the quantum-mechanical simulation is essential for applying nano-scale device structure.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.13-18
• /
• 2007

This paper presents the experimental findings on the different degradation mechanism which depends on the gate oxide thickness in lateral DMOS transistors. For thin oxide devices, the generation of interface states in the channel region and the trapped holes in the drift region is found to be the causes of the device degradation. For thick devices, the generation of interface states in the channel region is found to be the causes of the device degradation. We confirmed the different degradation mechanism using device simulation. From the comparison of device degradation under DC and AC stress, it is found that the device degradation is more significant under DC stress than one under AC stress. The device degradation under AC stress is more significant in high frequency. Therefore the hot carrier induced degradation should be more carefully considered in the design of RF LDMOS transistors and circuit design.

• KSBB Journal
• /
• v.18 no.5
• /
• pp.429-433
• /
• 2003

LAL (Limulus amebocyte lysate) test to detect and quantity endotoxin is based on gellation reaction between endotoxin and LAL from a blood extract of Limulus polyphemus. The test is labor intensive requiring dedicated personnel, takes relatively long reaction time (approximately 1 hr), requires relatively large volume of samples and reagents, and its end-point detection method is rather subjective. To solve these problems, we attempted to develop a miniaturized LOC (lab-on-a-chip) prototype using PDMS and glass. Using the 62 mm (length) ${\times}$ 18 mm (width) prototype in which 2 mm (width) ${\times}$ 44.34 mm (length) ${\times}$ 100 $\mu\textrm{m}$ (depth) microfluidic channel was provided, we compared the various detection methods of gellation, turbidometric, and chromogenic assays to find the chromogenic method to be the most suitable for small volume assay. In this assay, kinetic point method was more accurate than end point method. We also found the PDMS chip thickness should be minimized to around 2 mm to allow sufficient light transmittance, which necessitated a glass slide bonding for chip rigidity. Through the miniaturization, the test time was reduced from 1 hr to less than 10 minutes, and the sample volume could be reduced from 100 ${\mu}\ell$ to 4.4 ${\mu}\ell$. In sum, this study revealed that the mini LOC could be an alternative for a semi-automated and reliable method for LAL test.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2018.06a
• /
• pp.55-55
• /
• 2018

Recently, amorphous oxides such as InGaZnO (IGZO) and InZnO (IZO) as a channel layer of an oxide TFT have been attracted by advantages such as high mobility, good uniformity, and high transparency. In order to apply such an amorphous oxide TFTs to a display, the stability in various environments must be ensured. In the InGaZnO which has been studied in the past, Ga elements act as a suppressor of oxygen vacancy and result in a decreased mobility at the same time. Previous studies have been showed that the InZnO, which does not contain Ga, can achieve high mobility, but has relatively poor stability under various instability environments. In this study, the TFTs using $IZO/Al_2O_3$ double layer structure were studied. The introduction of an $Al_2O_3$ interlayer between source/drain and channel causes superior electrical characteristics and electrical stability as well as reduced contact resistance with optimally perfect ohmic contact. For the IZO and $Al_2O_3$ bilayer structures, the IZO 30nm IZO channels were prepared at $Ar:O_2=30:1$ by sputtering and the $Al_2O_3$ interlayer were depostied with various thickness by ALD at $150^{\circ}C$. The optimal sample exhibits considerably good TFT performance with $V_{th}$ of -3.3V and field effect mobility of $19.25cm^2/Vs$, and reduced $V_{th}$ shift under positive bias stress stability, compared to conventional IZO TFT. The enhanced TFT performances are closely related to the nice ohmic contact properties coming from the defect passivation of the IZO surface inducing charge traps, and we will provide the detail mechanism and model via electrical analysis and transmission line method.