• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.867-869
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• 2008

We have investigated the effects of hydrogen plasma treatment by PECVD (Plasma Enhanced Chemical Vapor Deposition) in the back channel region, the method for reducing the off state leakage current which increases with the short channel length of a-Si:H TFTs. To improve the off current characteristics, we analyzed the hydrogen plasma treatment with various RF power and plasma treatment times of PECVD. As the result of hydrogen plasma treatment in the back channel region it was remarkably reduced the off current level of 2um channel length TFT.

• ETRI Journal
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• 제20권1호
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• pp.16-27
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• 1998

In this paper, we consider the acquisition performance of an IS-95 reverse link access channel slot as a function of system design parameters such as postdetection integration length and the number of access channel message block repetitons. The uncertainty region of the reverse link spreading codes compared to that of forward link is very small, since the uncertainty region of the reverse link is determined by a cell radius. Thus, the parallel acquisiton technique in the reverse link is more efficient than a serial acquisition technique in terms of implementation and of acquisition time. The parallel acquisition is achieved by a bank of N parallel I/Q noncoherent correlator are analyzed for band-limited noise and the Rayleigh fast fading channel. The detection probability is derived for multiple correct code-phase offsets and multipath fading. The probability of no message error is derived when rake combining, access channel message block combining, and Viterbi decoding are applied. Numerical results provide the acquisition performance for system design parameters such as postdetection integration length and number of access channel message block repetitions in case of a random access on a mobile station.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1189-1192
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• 2009

Short channel a-Si:H TFT devices with Cu electrodes have been investigated. Short channel TFTs are defined by new plasma etch process. When the channel length becomes shorter, the TFT characteristics (threshold voltage, off current, sub threshold voltage, etc.,) are degraded. These degraded characteristics can be improved through the hydrogen plasma treatment and new gate insulator structure. Using these processes, 15.0 inch XGA LCD panel was fabricated successfully where the channel length of the TFT devices was about 2.5 micrometers.

• Transactions on Electrical and Electronic Materials
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• 제7권3호
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• pp.99-102
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• 2006

The electrical characteristics of CMOS inverter with LDMOSFET are studied for high power and digital circuit application by using two dimensional MEDICI simulator. The simulation is done in terms of voltage transfer characteristic and on-off switching properties of CMOS inverter with variation of channel length and channel doping levels. The channel which surrounds a junction-type source in LDMOSFET is considered to be an important parameter to decide a circuit operation of CMOS inverter. The digital logic levels of input voltage show to increase with increase of n-channel length and doping levels while the logic output levels show to the almost constant.

• 한국전기전자재료학회논문지
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• 제11권1호
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• pp.26-32
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• 1998

We have studied how the characteristics degradation between effective mobility and field effect mobility of gate channel in p-MOSFET's affects the gate channel length being follow by increased stress time and increased drain-source voltage stress. The experimental results between effective and field-effect mobility were analyzed that the measurement data are identical at the point of minimum slope in threshold voltage, the other part is different, that is, the effective mobility it the faster than the field-effect mobility. Also, It was found that the effective and field-effect mobility. Also, It was found that the effective and field-effect mobility of p-MOSFET's with short channel are increased by decreased channel length, increased stress time and increased drain-source voltage stress.

• E2M - 전기 전자와 첨단 소재
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• 제8권6호
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• pp.708-714
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• 1995

We have discussed the buried-channel(BC) behavior through the subthreshold characteristics of submicron PMOSFET device fabricated with twin well CMOS process. In this paper, we have guessed the initial conditions of ion implantation using process simulation, obtained the subthreshold characteristics as a function of process parameter variation such as threshold adjusting ion implant dose($D_c$), channel length(L), gate oxide thickness($T_ox$) and junction depth of source/drain($X_j$) using device simulation. The buried channel behavior with these process prarameter variation were showed apparent difference. Also, the fabricated pMOSFET device having different channel length represented good S.S value and low leakage current with increasing drain voltage.

• 한국재료학회지
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• 제18권5호
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• pp.272-276
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• 2008

In submicron MOSFET devices, maintaining the ratio between the channel length (L) and the channel depth (D) at 3 : 1 or larger is known to be critical in preventing deleterious short-channel effects. In this study, n-type SOI-MOSFETs with a channel length of $0.1\;{\mu}m$ and a Si film thickness (channel depth) of $0.033\;{\mu}m$ (L : D = 3 : 1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioning transistors on the very thin Si film, a protective layer of $0.08\;{\mu}m$-thick surface oxide was deposited prior to the source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron doping concentration of the Si film, in which the device channel is formed, was used as the key variable in the process simulation. The finished devices were electrically tested with a Medici device simulator. The result showed that, for a given channel doping concentration of $1.9{\sim}2.5\;{\times}\;10^{18}\;cm^{-3}$, the threshold voltage was $0.5{\sim}0.7\;V$, and the subthreshold swing was $70{\sim}80\;mV/dec$. These value ranges are all fairly reasonable and should form a 'magic region' in which SOI-MOSFETs run optimally.

• 한국관개배수논문집
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• 제21권1호
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• pp.118-126
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• 2014

In this study, the use of the spur of riverbank technique is being investigated. The spur of the riverbank typically reduces the velocity of flow and protects the embankments by increasing friction along the water and the banks. This also has an effect in the rise of water level upstream. It is also used for the rectification of riverside line and restoration of the waterway through sedimentation near the spur of the riverbank. In this study, physical-scaled experiments are conducted to investigate the process of creating a mild meandering channel using the spur of the riverbank with varying water flows and sedimentation functions. The hydraulics observations are taken with respect to the varying heights and length of the riverbank's spurs and the distance between each spur for the formation of the mild meandering channel. It is observed that for 1.06 times of the meander length, it requires 2 times of the interval with each spur of river width. Similarly, 1.25L times of the meander length, it requires 0.5 times of the interval with each spur of river width. The sand accumulation is induced by the spur of riverbank when the spur of riverbank's heights are more than 40% of water depth and the length of the spur of riverbank needs under than 20% of river width for avoid exaggerated sand accumulation in the center of channel.

• 한국산학기술학회논문지
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• 제11권5호
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• pp.1592-1596
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• 2010

IGZO (indium gallium zinc oxide) 박막트랜지스터는, 활성층 채널의 폭과 길이의 비가 고정된 경우에도, 채널 길이가 길어지면 게이트전압에 대한 드레인 전류의 특성곡선이 양의 전압 방향으로 이동하고 전계효과이동도는 낮아졌다. 채널의 길이와 폭이 고정된 상태에서는, 드레인이 전압 높은 경우에 전계효과이동도가 낮고 문턱아래 기울기가 큰 특성을 보였다. 이러한 현상은 IGZO 채널층의 일함수가 커서 소스/드레인 전극과 채널층의 접합부 띠굽음이 규소반도체의 경우와 반대방향으로 나타나는 것에 기인하는 것으로 해석된다.

• 전자공학회논문지T
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• 제35T권1호
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• pp.14-21
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• 1998

GaAs MESFET는 동작점에 따라 선형영역, 포화영역으로 구분된 모델을 사용함에 따라, GaAs MESFET 회로 해석을 위한 컴퓨터 시뮬레이션 시 영역의 경계점에서의 1차 및 2차 미분 불연속으로 인한 해의 발산 문제가 발생하곤 하였다. 본 논문에서는 선형영역과 포화영역을 모두 포함한 통합된 채널길이변조식을 제안하였다. 새로이 제안된 채널길이변조식을 이용하여 전류-전압 모델과 커패시턴스-전압 모델을 제안하였다. 제안된 전류-전압 모델은 Shur의 모델과 비교하였으며 제안된 커패시턴스-전압 모델은 디바이스 시뮬레이션 결과와 비교하였다. 비교된 결과로부터 제안된 모델들은 기존의 모델과 유사한 결과를 얻었으며 연속성이 개선될 것으로 기대된다.