• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.894-897
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• 2006

Spatial distribution of injected electrons and holes is evaluated by using single-junction charge pumping technique in SONOS(Poly-silicon/Oxide/Nitride/Oxide/Silicon) memory cells. Injected electron are limited to length of ONO(Oxide/Nitride/oxide) region in locally ONO stacked cell, while are spread widely along with channel in fully ONO stacked cell. Hot-holes are trapped into the oxide as well as the ONO stack in locally ONO stacked cell.

• Journal of the Semiconductor & Display Technology
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• v.2 no.2
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• pp.17-20
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• 2003

The current drive in an MOSFET is limited by the intrinsic channel resistance. All the other parasitic elements in a device structure playa significant role and degrade the device performance. These other resistances need to be less than 10%-20% of the channel resistance. To achieve the requirements, we should investigate a methodology of separation and quantification of those resistances. In this paper, we developed the extraction method of resistances using calibrated TCAD simulation. The resistance of the extension region is also partially determined by the formation of a surface accumulation region that forms under the gate in the tail region of the extension profile.

• Journal of information and communication convergence engineering
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• v.4 no.2
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• pp.84-87
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• 2006

Lateral distributions of locally injected electrons and holes in an oxide-nitride-oxide (ONO) dielectric stack of two different silicon-oxide-nitride-oxide-silicon (SONOS) memory cells are evaluated by single-junction charge pumping technique. Spatial distribution of electrons injected by channel hot electron (CHE) for programming is limited to length of the ONO region in a locally ONO stacked cell, while is spread widely along with channel in a fully ONO stacked cell. Hot-holes generated by band-to-band tunneling for erasing are trapped into the oxide as well as the ONO stack in the locally ONO stacked cell.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.344-345
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• 2012

The Gate-Induced-Drain-Leakage (GIDL) current with channel doping and width dependence are characterized. The GIDL currents are found to increase in MOSFETs with higher channel doping levels and the observed GIDL current is generated by the band-to-band-tunneling (BTBT) of electron through the reverse-biased channel-to-drain p-n junction. A BTBT model is used to fit the measured GIDL currents under different channel-doping levels. Good agreement is obtained between the modeled results and experimental data. The increase of the GIDL current at narrower widths in mainly caused by the stronger gate field at the edge of the shallow trench isolation (STI). As channel width decreases, a larger portion of the GIDL current is generated at the channel-isolation edge. Therefore, the stronger gate field at the channel-isolation edge causes the total unit-width GIDL current to increases for narrow-width devices.

• Journal of IKEEE
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• v.27 no.1
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• pp.45-52
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• 2023

Cold-junction correction(CJC) and disconnection detection circuit design of various thermocouples(TC) and multi-channel TC interface circuit using them were designed. The CJC and disconnection detection circuit consists of a CJC semiconductor device, an instrumentation amplifier(IA), two resistors and a diode for disconnection detection. Based on the basic circuit, a multi-channel interface circuit was also implemented. The CJC was implemented using compensation semiconductor and IA, and disconnection detection was detected by using two resistor and a diode so that IA input voltage became -0.42V. As a result of the experiment using R-type TC, the error of the designed circuit was reduced from 0.14mV to 3㎶ after CJC in the temperature range of 0℃ to 1400℃. In addition, it was confirmed that the output voltage of IA was saturated from 88mV to -14.2V when TC was disconnected from normal. The output voltage of the designed circuit was 0V to 10V in the temperature range of 0℃ to 1400℃. The results of the 4-channel interface experiment using R-type TC were almost identical to the CJC and disconnection detection results for each channel. The implemented multi-channel interface has a feature that can be applied equally to E, J, K, T, R, and S-type TCs by changing the terminals of CJC semiconductor devices and adjusting the IA gain.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.94-94
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• 2008

We have performed simulation for Junction Field Effect Transistor(JFET) using Silvco to improve its electrical properties. The device structure and process conditions of Si-control JFET(Si-JFET) were determined to set its cut off voltage and drain current(at Vg=0V) to -0.5V and $300{\mu}A$, respectively. From electrical property obtained at various implantation energy, dose, and drive-in conditions of p-gate doping, we found that the drive in time of p-type gate was the most determinant factor due to severe diffusion. Therefore we newly designed SiGe-JFET, in which SiGe layer is to epitaxial layers placed above and underneath of the Si-channel. The presence of SiGe layer lessen the p-type dopants (Boron) into the n-type Si channel the phenomenon would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer will be discussed in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.4
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• pp.227-236
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• 2016

In the present experimental study, the effect of gas- and liquid-injected methods on the formation of bubble and liquid slug at the merging micro T-junction of a square microchannel with dimensions $600{\mu}m{\times}600{\mu}m$ was investigated. Nitrogen and water were used as test fluids. The superficial velocities of the liquid and gas were in the range of 0.05 - 1 m/s, and 0.1 - 1 m/s, respectively, where the Taylor flow was observed. The bubble length, liquid slug length, bubble velocity, and bubble generation frequency were measured by analyzing the images captured using a high-speed camera. Under similar inlet superficial velocity conditions, in the case of gas injection to the main channel at the merging T-junction (T_gas-liquid), the lengths of the bubble and liquid slug were longer, and the bubble generation frequency was lower than in the case of liquid injection to the main channel at the merging T-junction (T_liquid-gas). On the other hand, in both cases, the bubble velocity was almost the same. The previous correlation proposed using experimental data for T_liquid-gas had predicted the present experimental data of bubble length, bubble velocity, liquid slug length, and bubble generation frequency for T_gas-liquid to be ~24%, ~9%, ~39%, ~55%, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.11
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• pp.1290-1298
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• 1992

In this paper, the Poisson's equation is solved two-dimensionally without employing any fitting parameters, and the model formulation of a short-channel MOSFET is accomplished fully analytically. It automatically derives a very accurate drain current expression that can be used simultaneously for strong inversion, subthreshold, and saturation regions. Furthermore, this model gives a unified explanation for the short-channel effect, the body effect, the DIBL effect, and even the variation of the effective carrier mobility. The obtained expression of the threshold voltage also includes the dependence on the oxide thickness, the n+ junction depth, and temperature.

• Transactions on Electrical and Electronic Materials
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• v.7 no.3
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• pp.99-102
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• 2006

The electrical characteristics of CMOS inverter with LDMOSFET are studied for high power and digital circuit application by using two dimensional MEDICI simulator. The simulation is done in terms of voltage transfer characteristic and on-off switching properties of CMOS inverter with variation of channel length and channel doping levels. The channel which surrounds a junction-type source in LDMOSFET is considered to be an important parameter to decide a circuit operation of CMOS inverter. The digital logic levels of input voltage show to increase with increase of n-channel length and doping levels while the logic output levels show to the almost constant.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.708-714
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• 1995

We have discussed the buried-channel(BC) behavior through the subthreshold characteristics of submicron PMOSFET device fabricated with twin well CMOS process. In this paper, we have guessed the initial conditions of ion implantation using process simulation, obtained the subthreshold characteristics as a function of process parameter variation such as threshold adjusting ion implant dose($D_c$), channel length(L), gate oxide thickness($T_ox$) and junction depth of source/drain($X_j$) using device simulation. The buried channel behavior with these process prarameter variation were showed apparent difference. Also, the fabricated pMOSFET device having different channel length represented good S.S value and low leakage current with increasing drain voltage.