• Title/Summary/Keyword: Cell-chip

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Biodevice Technology (바이오소자 기술)

  • Choi, Jeong-Woo;Lee, Bum-Hwan
    • Korean Chemical Engineering Research
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    • v.44 no.1
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    • pp.1-9
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    • 2006
  • Biodevices composed of biomolecular layer by mimicking the natural functions of cells and the interaction mechanisms of the constituted biomolecules have been developed in various industrial fields such as medical diagnosis, drug screening, electronic device, bioprocess, and environmental pollution detection. To construct biodevices such as bioelectronic devices (biomolecular diode, bio-information storage device and bioelectroluminescence device), protein chip, DNA chip, and cell chip, biomolecules including DNA, protein, and cells have been used. Fusion technology consisting of immobilization technology of biomolecules, micro/nano-scale patterning, detection technology, and MEMs technology has been used to construct the biodevices. Recently, nanotechnology has been applied to construct nano-biodevices. In this paper, the current technology status of biodevice including its fabrication technology and applications is described and the future development direction is proposed.

Design of a High Speed Asymmetric Baseband MODEM ASIC Chip for CATV Network (CATV 망용 고속 비대칭 기저대역 모뎀 ASIC 칩 설계)

  • 박기혁
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.9A
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    • pp.1332-1339
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    • 2000
  • This paper presents the architecture and design of a high speed asymmetric data transmission baseband MODEM ASIC chip for CATV networks. The implemented MODEM chip supports the physical layer of the DOCSIS(Data Over Cable Service Interface Specification) standard in MCNS(Multimedia Cable Network System) The chip consists of a QPSK/16-QAM transmitter and a 64/256-QAM receiver which contain a symbol timing recovery circuit, a carrier recovery circuit, a blind equalizer using MMA and LMS algorithms. The chip can support data rates of 64Mbps at 256 QAM and 48Mbps at 64-QAM and can provide symbol rates up to 8MBaud. This symbol rate is faster than existing QAM receivers. We have performed logic synthesis using the $0.35\mu\textrm{m}$ standard cell library. The total number of gates is about 290,000 and the implemented chip is being fabricated and will be delivered soon.

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Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application

  • Lee, Jung-Hwan;Jeon, Seong-Do;Chang, Sung-Keun
    • ETRI Journal
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    • v.26 no.6
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    • pp.583-588
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    • 2004
  • In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

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P&R Porting & Test-chip implementation Using Standard Cell Libraries (표준 셀 라이브러리 P&R 포팅과 테스트 칩의 설계)

  • Lim, Ho-Min;Kim, Nam-Sub;Kim, Jin-Sang;Cho, Won-Kyung
    • Journal of Advanced Navigation Technology
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    • v.7 no.2
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    • pp.206-210
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    • 2003
  • In this paper, we design standard cell libraries using the 0.18um deep submircom CMOS process, and port them into a P&R (Placement and Routing) CAD tool. A simple test chip has been designed in order to verify the functionalities of the 0.18um standard cell libraries whose technical process was provided by Anam semiconductor. Through these experiments, we have found that the new 0.18um CMOS process can be successfully applied to automatic digital system design.

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Detection of Bacillus Cereus Using Bioluminescence Assay with Cell Wall-binding Domain Conjugated Magnetic Nanoparticles

  • Park, Chanyong;Kong, Minsuk;Lee, Ju-Hoon;Ryu, Sangryeol;Park, Sungsu
    • BioChip Journal
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    • v.12 no.4
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    • pp.287-293
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    • 2018
  • Bacillus cereus can cause blood infections (i.e., sepsis). Its early detection is very important for treating patients. However, an antibody with high binding affinity to B. cereus is not currently available. Bacteriophage cell wall-binding domain (CBD) has strong and specific binding affinity to B. cereus. Here, we report the improvement in the sensitivity of an ATP bioluminescence assay for B. cereus detection using CBD-conjugated magnetic nanoparticles (CBD-MNPs). The assay was able to detect as few as 10 colony forming units (CFU) per mL and $10^3CFU\;per\;mL$ in buffer and blood. CBD-MNPs did not show any cross-reactivity with other microorganisms. These results demonstrate the feasibility of the ATP assay for the detection of B. cereus.

Electroporation and Viability Monitoring Chip for Lung Cancer Cells in Single Channel with Multiple Electric Field Zones (다수의 전기장 분포가 생성되는 단일 미세유로를 이용한 폐암세포 전기천공 및 활성도 분석칩)

  • Kim, Min-Ji;Kim, Tae-Yoon;Cho, Young-Ho
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.36 no.9
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    • pp.901-905
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    • 2012
  • We present an electroporation and viability monitoring chip for lung cancer cells in a single channel with multiple electric field zones. Previous electroporation chips utilized multiple microchannels or electrodes to form multiple electric fields, thus resulting in complex structures. However, the present chip can generate multiple electric fields in a single stepwise microchannel between a pair of electrodes, thus achieving the analysis of both cell electroporation and viability with a simple structure. We demonstrate that the electric field of 0.4 kV/cm results in a maximum percentage of $51.4{\pm}3.0%$ and $26.6{\pm}0.7%$ of viable and electroporated human lung cancer cells, H23 and A549, respectively. The present chip has potential for use in integrated cell chips for transfection studies.

The Design and Implementation of SSPA(Solid State Power Amplifier) using chip device (Chip소자를 이용한 SSPA 설계 및 제작에 관한 연구)

  • Kim Yong-Hwan;Min Jun-ki;Kim HyunJin;Yoo Hyeong-soo;Lee Hyeong-kyu;Hong Ui-seok
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.2 no.2 s.3
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    • pp.65-72
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    • 2003
  • In this work a 6-stage hybrid power amplifier which can be used for the wireless communication systems for MMC(hficrowave Micro Cell) and ITS wireless communication system is designed and fabricated. Ihe power amplifier's each stages was fabricated Hetero-junction Power FET of bare chip type and an alumina substrate with $\varepsilon_{r}$=9.9 and 15-mil thickness. The measured results of power amplifier module showed 33.2$\~$36.5 dB small signal gain, 33.0$\~$34.0 dBm output power at forward frequency (17.6 GHa $\~$ 17.9 CHz) and 36.0$\~$37.0 dB small signal gain, 33.0$\~$34.5 dBm output power at reverse frequency (19.0 GHz $\~$19.2GHz).

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Design of a Cell Verification Module for Large-density EEPROM Memories (대용량 EEPROM 메모리 셀 검증용 모듈 회로 설계)

  • Park, Heon;Jin, RiJun;Ha, Pan-Bong;Kim, Young-Hee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.10 no.2
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    • pp.176-183
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    • 2017
  • There is a problem of long erase and program times in testing large-density memories. Also, there is a need of testing the VT voltages of EEPROM cells at each step during the reliability test. In this paper, a cell verification module is designed for a 512kb EEPROM and a CG (control gate) driver is proposed for measuring the VT voltages of a split gate EEPROM having negative erase VT voltages. In the proposed cell verification module, asymmetric isolated HV (high-voltage) NMOS devices are used to apply negative voltages of -3V to 0V in measuring erase VT voltages. Since erasing and programming can be done in units of even pages, odd pages, or a chip in the test time reduction mode, test time can be reduced to 2ms in testing the chip from 4ms in testing the even and the odd pages.

A New Design of Blood Cell Counter using DSP chip and Optimal Discrimination Method (DSP 칩과 최적분별법을 이용한 새로운 혈구입자 계수기 설계)

  • Kim, G.H.;Kim, J.W.;Kim, K.S.;Hong, W.H.;Kim, S.H.
    • Proceedings of the KOSOMBE Conference
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    • v.1991 no.05
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    • pp.89-93
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    • 1991
  • The purpose of this reserch is to design the blood cell counting instrument which can measure the number of RBC(Red Blood Cell) and WBC(White Blood Cell) including many other blood component. The proposed method uses the electrical impedence method and the new discrimination method wi th DSP chip and software algorithm. The system consist of control unit, blood cell discrimination unit, hemoglobin spectrometer, post detect ion processor unit, and IBM-PC interface unit. In this paper, the discrimination system has been implemented using digital signal processor, which result in the reduction of system hardware and cost. The system is helpful in providing necessary clinical test for screen test and quality control of hematology.

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Forensic Data Acquisition on Cell Phone using JTAG Interface (JTAG을 이용한 휴대폰 포렌식 데이터 수집)

  • Kim, Keon-Woo;Ryu, Jae-Cheol
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.333-334
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    • 2008
  • With the role of cell phones in today's society as a digital personal assistant as well as the primary tool for personal communication, it is possible to imagine the involvement of cell phones in almost any type of crime. The progression of a criminal investigation can hinge on vital clues obtained from a cell phone. This paper will be concentrated on CDMA system phones and focus on the data extraction for cell phone forensics. Especially, the data acquisition method of JTAG interface access to memory chip will be covered.

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