• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.4
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• pp.218-221
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• 2015

Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. In this study we have investigated a structure to reduce the on-resistance characteristics of the MOSFET. We have a proposed MOSFET structure of active cells region buried under the gate pad. The measurement are carried out with a EDS to analyze electrical characteristics, and the proposed MOSFET are compared with the conventional MOSFET. The result of proposed MOSFET was 1.68[${\Omega}$], showing 10% improvement compared to the conventional MOSFET at 700[V].

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.5
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• pp.1-5
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• 1975

접합형 트린지스터와 발광다이오드(LED) 및 광도전소자(CdS)로서 구성된 광결합 전류안정부저항회로를 진안하였다. 이는 일반적으로 광트랜지스터보다도 더 예민한 것을 이용하여, CdS와 LED를 밀착 시켜서 LED에 흐르는 전류와 CdS의 실효저항변화로써 결합된 광결합방식을 택하였다. 트랜지스터의 콜랙터-에미터간에 인위적인 누변저항을 삽입하는 방법을 도입함으로써 부저항치 및 최대입력단자전압치를 임의로 변화할 수 있게 하였으며, 제안한 회로를 분석하고 또 이를 실험적으로 확인하였다. 누변저항을 1KΩ에서 30KΩ까지 변화시켰을 때 최대입력단자전압은 1.65V에서 4.22V로 변하였고, 부저항치는 -1.0KΩ에서 -10.0KΩ까지 변하였다. 또 실험치에 대한 계산치에의 상대백분최대오차가 11%이었다. A current stable negative resistance circuit has been constucted with combination of coulplementary symmetrical transistors, a light emitting diode and a photoconductive cell. The negative resistance(Rn) and break-over voltage(VBo) can be set at a designed value according to adjustment of the artificial leakage resistance of p-n-p transistor. The RN and VBo calculated in this designed circuit are checked though the experiments, the errors are found less than 11%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.88-94
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• 2011

In this paper, we design a 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the non-programmed eFuse is reduced from 728 ${\mu}A$ to 61 ${\mu}A$ when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 $k{\Omega}$ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier).

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.15.2-15.2
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• 2009

Manufacturing of printed electronics using printing technology has begun to get into the hot issue in many ways due to the low cost effectiveness to existing semi-conductor process. This technology with both low cost and high productivity, can be applied in the production of organic thin film transistor (OTFT), solar cell, radio frequency identification (RFID) tag, printed battery, E-paper, touch screen panel, black matrix for liquid crystal display (LCD), flexible display, and so forth. The emerging technology to manufacture the products in mass production is roll-to-roll printing technology which is a manufacturing method by printings of multi-layered patterns composed of semi-conductive, dielectric and conductive layers. In contrary to the conventional printing machines in which printing precision is about $50~100{\mu}m$, the printing machines for printed electronics should have a precision under $30{\mu}m$. In general, in order to implement printed electronics, narrow width and gap printing, register of multi-layer printing by several printing units, and printing accuracy of under $30{\mu}m$ are all required. We developed the roll-to-roll printing equipment used for printed electronics, which is composed of un-winder, re-winder, tension measurement system, feeding units, dancer systems, guide unit, printing unit, vision system, dryer units, and various auxiliary devices. The equipment is designed based on cantilever type in which all rollers except printing ones have cantilever types, which could give more accurate machine precision as well as convenience for changing rollers and observing the process.

• Transactions on Electrical and Electronic Materials
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• v.12 no.6
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• pp.258-261
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• 2011

A ferroelectric $(Bi,La)_4Ti_3O_{12}$ (BLT) thin film fabricated by the pulsed-DC sputtering method was evaluated on a cell structure to check its compatibility to high density ferroelectric random access memory (FeRAM) devices. The BLT composition in the sputtering target was $Bi_{4.8}La_{1.0}Ti_{3.0}O_{12}$. Firstly, a BLT film was deposited on a buried Pt/$IrO_x$/Ir bottom electrode stack with W-plug connected to the transistor in a lower place. Then, the film was finally crystallized at $700^{\circ}C$ for 30 seconds in oxygen ambient. The annealed BLT layer was found to have randomly oriented and small ellipsoidal-shaped grains (long direction: ~100 nm, short direction: ~20 nm). The small and uniform-sized grains with random orientations were considered to be suitable for high density FeRAM devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.189.2-189.2
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• 2013

1차원 산화아연 나노구조물은 광대역 에너지 밴드갭(~3.3 eV)과 독특한 물리적 특성을 갖고 있어, 전계효과 트랜지스터(field effect transistor), 발광다이오드(light emitting diode), 자외선 광검출기 (ultraviolet photodetector) 및 태양전지(photovoltaic cell)에 널리 이용되고 있다. 특히, 1차원 산화아연 나노구조물은 직접천이형 에너지 밴드갭(direct bandgap)을 갖고 있으며, 빛으로부터 여기된 전자가 1차원 나노구조물을 통해 향상된 이동경로를 제공할 수 있어서 차세대 자외선 광검출기 응용에 대한 연구가 활발히 진행되고 있다. 한편, 수열합성법(hydrothermal method)을 통해서 1차원 산화아연 나노구조물을 비교적 간단하고 저온공정을 통해서 합성할 수 있는데, 이를 광검출기 소자구조에 응용에서 양전극에 연결하기 위해서는 복잡하고 정교한 공정이 필요하다. 이에 본 연구에서는 수열합성법을 통해 합성된 산화아연 나노로드가 포함된 에탄올 용액을 금(Au) 패턴에 drop-casting을 통해서 간단한 방법으로 metal-semiconductor-metal (MSM) 광검출기를 제작하여 광반응 특성을 분석하였다. 또한 염료를 통해 가시광을 흡수하여 광전류(photocurrent)를 발생시킬 수 있도록 염료를 흡착한 산화아연 나노로드를 이용하여 같은 구조의 MSM 광검출기를 제작하여 가시광에 대한 광반응 특성을 관찰하였다.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1469-1479
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• 2017

Primary-side regulation (PSR) scheme is widely applied in low power applications, such as cell phone chargers, network adapters, and LED drivers. However, the efficiency and standby power requirements have been improved to a high standard due to the new trends of DOE (Department Of Energy) Level VI and COC (Code Of Conduct specifications) V5. The major drawbacks of PSR include poor regulation due to inaccurate feedback and difficulty in acquiring acceptable regulation. A novel adaptive blanking strategy for constant current and constant voltage regulation is proposed in this paper. An accurate model for the sample blanking time related to transformer leakage inductance and the metal-oxide-semiconductor field-effect transistor (MOSFET) parasitic capacitance is established. The proposed strategy can achieve accurate detection for ultra-low standby power. In addition, numerous control factors are analyzed in detail to eliminate the influence of leakage inductance on the loop stability. A dedicated controller integrated circuit (IC) with a power MOSFET is fabricated to verify the effectiveness of the proposed control strategy. Experimental results demonstrated that the prototype based on the proposed IC has excellent performance.

• Journal of Korea Society of Digital Industry and Information Management
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• v.19 no.2
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• pp.11-25
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• 2023

With the increasing advancement of VLSI technology, health care system is also developing to serve the humanity with better care. Therefore, biomedical implantable devices are one of the amazing important invention of scientist to collect data from the body cell for the diagnosis of diseases without any pain. This Biomedical implantable transceiver circuit has several important issues. Oscillator is one of them. For the design flexibility and complete transistor-based architecture ring oscillator is favorite to the oscillator circuit designer. This paper represents the design and analysis of the a 9-stage CMOS ring oscillator using cadence virtuoso tool in 180nm technology. It is also designed to generate the carrier signal of 403.5MHz frequency. Ring oscillator comprises of odd number of stages with a feedback circuit forming a closed loop. This circuit was designed with 9-stages of delay inverter and simulated for various parameters such as delay, phase noise or jitter and power consumption. The average power consumption for this oscillator is 9.32㎼ and average phase noise is only -86 dBc/Hz with the source voltage of 0.8827V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.687-691
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• 2011

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory in consideration of EM (electro-migration) and eFuse resistance variation based on a $0.18{\mu}m$ generic process, which is used for an analog trimming application. First, we use an external program voltage to increase the program power applied an eFuse. Secondly, we apply a scheme of precharging BL to VSS prior to RWL (read word line) activation and optimize read NMOS transistors to reduce the read current flowing through a non-programmed cell. Thirdly, we design a sensing margin test circuit with a variable pull-up load out of consideration for the eFuse resistance variation of a programmed eFuse. Finally, we increase program yield of eFuse OTP memory by splitting the length of an eFuse link.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7B
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• pp.647-659
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• 2003

LPM(Longest Prefix Matching)searching in If address lookup is a major bottleneck of IP packet processing in the high speed router. In the conventional lookup table for the LPM searching in CAM(Content Addressable Memory) the complexity of fast update take 0(1). In this paper, we designed pipeline architecture for fast update of 0(1) cycle of lookup table and high throughput and low area complexity on LPM searching. Lookup-table architecture was designed by CAM(Content Addressable Memory)away that uses 1bit RAM(Random Access Memory)cell. It has three pipeline stages. Its LPM searching rate is affected by both the number of key field blocks in stage 1 and stage 2, and distribution of matching Point. The RTL(Register Transistor Level) design is carried out using Verilog-HDL. The functional verification is thoroughly done at the gate level using 0.35${\mu}{\textrm}{m}$ CMOS SEC standard cell library.