• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.5
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• pp.52-59
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• 1996

The boroadband ISDN will transprot the traffics for a wide range of applications with different quality-of-service (QOS) requirements and the priorit control mechanism is an effective method to support multiple classes of services. This paper proposes a new mechanism to satisfy simultaneously the different levels of cell loss performance for the two classes of heterogeneous nonreal-time ATM traffics as well as the delay and loss requirements of real-time traffics. Its performance is analyzed using the stochastic integral approach with the cell arrivals of input streams modeled as markov modulated poisson processes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.407-410
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• 1999

Viterbi decoder is implemented with a Radix-4 architecture at 0.5$\mu\textrm{m}$ process even though the delay time of standard tell is big and it causes a bigger chip size. As process develops, the delay time of standard cells is getting smaller. Therefore, the requirement of speed and chip size is satisfied by using Radix-2 algorithm to implement Viterbi decoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1503-1513
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• 1998

This paper is related to a performance analysis of B-NT system, which is essential compositional equipment of B-ISDN access network. A simulator enabling performance analysis according to the change of network configuration topology and the change of user traffic is developed in this study. The developed B-NT, system simulator consists of graphic user interface module, simulation program automatic generator module, and B-NT system model library module. As examples of the results of performance analysis using the simulator, end-to-end user cell transmission delay time, queueing delay time in each system, and cell loss rate in the head node switch are presented. The simulator developed in this paper can be utilized in determining the network topology of B-NT system.

• Journal of IKEEE
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• v.20 no.2
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• pp.167-170
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• 2016

Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, $T_{SAE}$. The variation of $T_{SAE}$ makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay ($RBL_{conv}$), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing $T_{SAE}$ variation are briefly introduced, and the maximum possible number of on-cell which can satisfy $6{\sigma}$ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than $RBL_{conv}$ and energy consumption is reduced which 8% and 32.4% than $RBL_{conv}$.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.95-98
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• 1998

In this paper, we propose a cell scheduling algorithm for ABR traffic in ATM multiplexer. Proposed Algorithm can support ABR service more efficiently than existing WRR and DWRR algorithm. We evaluate the performances of proposed algorithm through computer simulation. Also, we model the VBR and the ABR traffics as ON/OFF source, and the CBR traffic as a Poisson source. And the simulation shows that proposed algorithm better performance over other cell scheduling algorithm in tem of mean cell delay time.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.85-88
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• 2002

Maintaining a proper level of cell lead, system throughput can be maximized by a transmission rate control over the uplink in DS/CDMA cellular system to support integrated services of real-time and delay-tolerant traffic. We find that the cell load-based rate control scheme can be further enhanced by taking the varying channel condition into account In conjunction with some fair scheduling algorithm. Our simulation results show that the proposed scheme outperforms the original cell load-based rate control with the round-robin sharing scheduling scheme.

• Korean Journal of Construction Engineering and Management
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• v.12 no.6
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• pp.31-41
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• 2011

Since the cases of time extension have continuously transpired in the public construction project, the potential of economical loss and claims is increasing because the concerned parties such as an owner or a contractor have not properly performed their own responsibility for time extension. One of the main reasons is that the present planning and scheduling do not support the method to apportion the proper responsibility to the right party. This problem has repeatedly led to time extension and made it difficult for the concerned parties to perform the responsibility for time extension. In order to overcome this problem, a framework of delay administration is required as the method to apportion the proper responsibility to the right party. To solve this problem, this paper aimed to develop the conceptual model and prototype system as the practical method to administrate delay causation. Furthermore, the verification result for the reliability and applicability throughout the case studies on real construction projects shows that the conceptual model and prototype system developed would help efficiently to administrate the delay causation.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.137-143
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• 2015

A delay-line type time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) is most widely owing due to its simple structure and high conversion rate. However, the delay-line type TDC suffers from nonlinearity error caused by the long delay-line because its time interval measurement range is determined by the length of the used delay line. In this study, a new TDC structure with a shorter delay line by taking a pulse train as an input is proposed for improved time accuracy and efficient use of resources. The proposed TDC utilizes a pulse-train with four transitions and a transition state detector that identifies the used transition among four transitions and prevents the meta-stable state without a synchronizer. With 72 delay cells, the measured resolution and maximum non-linearity were 20.53 ps, and 1.46 LSB, respectively, and the time interval measurement range was 5070 ps which was enhanced by approximately 343 % compared to the conventional delay-line type TDC.

• The Transactions of the Korea Information Processing Society
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• v.3 no.2
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• pp.295-304
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• 1996

Toprovide economical BISDN service, with which integration process of many types of media is possible, it is necessary to construct a system with ground network and satellite network combined. The method for this type of transmission using satellite is TDMA that can provide services to many users in various area. However, the most difficult task to connect TDMA which uses synchronous method to ATM which used asynchronous transfer mode is the deterioration n of ATM transmission quality such as cell delay variation. Therefore, it is necessary to develop delay variation compensation method which can confront to the ATM. Efficient ways to use satellite links under the conditions such that maximum efficiency of the delay variation is limited under the required value, and the burst characteristic of transmission cell does not increase are being researched for translation between in ATM and TDMA. This paper points out the problems when time stamp method, reviewd in ground network, is applied to the satellite links to compensate the delay variation .To solve the problem, discrete cell count method is introduced along with the calculation of transmission capacity and error rate.Also, from the observation of stab-ility of the system and verification of reliability even when singal error occurred in the cell transmission timing information, the proposed compensation method appeared to be excellent.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.109-118
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• 2007

As the integration density and the operating speed of System on Chips (SoCs) become increasingly high, it is crucial to test delay defects on the SoCs. This paper introduces an enhanced IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller for the wrapper interface logic, and proposes a transition delay fault test method. The method proposed can detect slow-to-rise and slow-to-fall faults sequentially with low area overhead and short test time. and simultaneously test IEEE 1500 wrapped cores operating at different core clocks.