• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.648-653
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• 2011

In this paper, coordinated space division multiple access(SDMA) technology is proposed to mitigate inter-cell interference by using partial channel state information in cooperative wireless communications system with limited feedback. Each AT selects an optimal cluster transmission mode and sends it back to a cluster scheduler, and at the cluster scheduler, ATs are scheduled within a AT group with the identical cluster transmission mode, and the optimal transmission mode and the corresponding scheduled ATs are determined to maximize scheduling priority. Also, in order to enhance multiuser diversity gain, an extended transmission feedback method is proposed to feed back multiple preferred cluster transmission modes at each AT. It is shown that the proposed coordinated SDMA scheme outperforms existing non-coordinated SDMA schemes in terms of the average system throughput.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.377-379
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• 1998

고속의 입력 큐를 가진 스위치는 출력 큐를 가진 스위치보다 더 경제적이며 단순하다고 알려져 있다. 그러나 입력 큐를 가진 스위치는 성능을 크게 저하시키는 HOL Blocking이라는 문제를 가지고 있다. 입력 큐 스위치는 랜덤 어세스 입력 큐와 셀 스케쥴링 알고리즘을 사용한다면 휠씬 좋은 성능을 얻을 수 있다. 많은 입력 큐 ATM 스위치의 Self-Firing셀 스케쥴러가 제안되어 왔으나, 여러 가지 입력포트와 분포에서 측정된 성능이 서로 크게 차이가 난다는 점에서 공정하지 못한 것이었다. 본 논문에서 우리는 어떠한 트애픽 분포에서도 공정성을 가지는 셀 스케쥴러를 제안하며, 제안한 스케쥴러가 비록 트래픽이 비균일 분포일지라도 공정성이 유지되는 것을 모의 실험을 통하여 증명한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.294-298
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• 1998

ATM망에서는 악의의 가입자가 협상된 대역폭 이상을 사용하여 발생하는 망의 폭주에 의해 선의의 가입자의 서비스 품질이 저하되는 것을 방지하기 위해 사용자 파라메터 감시를 수행한다. 그런데 사용자가 대역폭을 준수하여 셀을 전송한다고 하더라도 교환기, 다중화기둥을 거치면서 여러 연결의 셀들이 다중화 되면 CDV가 발생하여 사용자 파라메터 감시를 수행하는 장치에서 대역폭 위반으로 검출하여 셀이 손실되거나 셀 전달 우선 순위가 변경되어 서비스의 품질이 저하 될 수 있다. 이를 방지하기 위해 망의 장치는 셀을 출력할 때 장치에서 발생된 CDV를 보상하여 원래의 셀 스트림의 형태를 복원하여 전송함으로써 서비스 품질의 저하를 방지한다. 이를 스페이서라고 하는데, 본 논문에서는 이러한 스페이서의 구현 방식을 살펴보고, 메모리가 적게 사용되는 셀 도착 구동 방식의 스페이서 구조를 제안하고 실험을 통해서 그 성능을 평가하였다.

• Journal of Institute of Control, Robotics and Systems
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• v.4 no.5
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• pp.651-657
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• 1998

In this study, an intelligent scheduling with hybrid architecture, which integrates expert system and neural network, is proposed. Neural network is trained with the data acquired from simulation model of FMC to obtain the knowledge about the relationship between the state of the FMC and its best dispatching rule. Expert system controls the scheduling of FMC by integrating the output of neural network, the states of FMS, and user input. By applying the hybrid system to a scheduling problem, the human knowledge on scheduling and the generation of non-logical knowledge by machine teaming, can be processed in one scheduler. The computer simulation shows that comparing with MST(Minimum Slack Time), there is a little increment in tardness, 5% growth in flow time. And at breakdown, tardness is not increased by expert system comparing with EDD(Earliest Due Date).

• IE interfaces
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• v.15 no.4
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• pp.325-337
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• 2002

In this study we consider the problem of production planning of TFT-LCD(Thin Film Transistor - Liquid Crystal Display) production factory. Due to the complexities of the TFT-LCD production processes, it is difficult to schedule the production planning, and the study about automated scheduler is insufficient. In addition, the existing production method is a Push-System to raise the operation rate with expensive equipment, that has the problem to satisfy the due-date. This study presents an algorithm having a concept of Pull-System that satisfies the due-date and considers specialties of TFT-LCD production process. We make MPS(Master Production Schedule) according to the sales order, and present algorithms for scheduling about In/Out plan considering factory capacity, line balancing, material requirement, and inventory level of all Array, Cell, and Module processes. These algorithms are integrated as an automated production system, and we implement them in the actual TFT-LCD factory circumstance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.10
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• pp.929-937
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• 2012

In this paper, we introduce three types of opportunistic interference management strategies in multi-cell uplink networks with time-invariant channel coefficients. First, we propose two types of opportunistic interference mitigation techniques, where each base station (BS) opportunistically selects a set of users who generate the minimum interference to the other BSs, and then their performance is analyzed in terms of degrees-of-freedom (DoF). Second, we propose a distributed opportunistic scheduling, where each BS opportunistically select a user using a scheduler designed based on two threshold, and then its performance is analyzed in terms of throughput scaling law. Finally, numerical evaluation is performed to verify our result.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.423-428
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• 2008

We consider the use of cooperative diversity in a multiuser wireless data network. This paper provides an analysis of the interaction between cooperative diversity and multiuser diversity on downlink channels. By using approximation of the signal-to-noise ratio (SNR) distribution of each cooperative diversity link by Gamma distribution, an analytic expression is derived for the average throughput of a single-cell wireless system with multiple cooperative diversity links combined with a fair-access scheduler. The proposed analytic approach is verified through comparisons with simulated results and shows that cooperative diversity makes the detrimental impacts on multiuser diversity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.3
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• pp.586-597
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• 2004

MAC (Medium Access Control) protocol is necessary for a OLT (Optical Line Termination) to allocate bandwidth to ONUs (Optical Network Units) dynamically in ATM PON (Passive Optical Network) operated in a kind of optical subscriber network having tree topology. The OLT collect information about ONUs and provide all permission with each ONU effectively by means of MAC protocol. Major functions of MAC protocol are composed of the algorism for distributing permission demanded by a ONU dynamically and allocation all permission used in APON properly. Sometimes MAC get to be a element of limiting the whole operation speed and occupy a most frequent operation part of the TC (Transmission Convergence) function module so it have to be designed to guarantee the best quality for each traffic. This paper introduce the way of implementation of a algorism which satisfy all of the upper renditions. This MAC algorism allocate bandwidth according to a number of working ONU and the information of the queue length dynamically and distribute permission for same interval to minimize delay variation of each ONU cell. MAC scheduler for the dynamic bandwidth allocation which is introduced in this paper has look-up table structure that makes programming possible. This structure is very suitable for implementation and operated in high speed because it require very simple and small chip size.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.