• Title/Summary/Keyword: Cell Buffer

Search Result 703, Processing Time 0.03 seconds

A cell scheduling of a logically separated buffer in ATM switch (ATM 스위치에서 논리적으로 분할된 버퍼의 셀 스케쥴링)

  • 구창회;나지하;박권철;박광채
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.22 no.8
    • /
    • pp.1755-1764
    • /
    • 1997
  • In this paper, we proposed the mechanism for the buffer allocation and a cell scheduling method with logical separation a single buffer in the ATm switch, and analyzed the cell loss probability and the delay of each trafic (CBR/VBR/ABR) based on the weighted value and the dynamic cell service scheduling algorithm. The proposed switch buffering system classifies composite trafics incoming to the switch, according to the characteristic of traffic, then stores them in the logically separated buffers, and adopts the round-robin service with weighted value in order to transmit cells in buffers though one output port. We analyzed 4 cell service scheduling algorithms with dynamic round-robinfor each logically separated service line of a single buffer, in which buffers have the respective weighted values and 3 classes on mixed traffic which characteristized by traffic descriptor. In simulation, using SIMCRIPT II.5., we model the VBR and the ABR traffics as ON/OFF processes, and the CBR traffic as a Poisson processes. As the results of analysis according to the proposed buffer management mechanism and cell service algorithm, we have found that the required QoS of each VC can be quaranteed depends on a scale of weighted values allocated to buffers that changed the weighted values, and cell scheduling algorithm.

  • PDF

Biochemical Properties and Localization of the β-Expansin OsEXPB3 in Rice (Oryza sativa L.)

  • Lee, Yi;Choi, Dongsu
    • Molecules and Cells
    • /
    • v.20 no.1
    • /
    • pp.119-126
    • /
    • 2005
  • ${\alpha}$-Expansins are bound to the cell wall of plants and can be solubilized with an extraction buffer containing 1 M NaCl. Localization of ${\alpha}$-expansins in the cell wall was confirmed by immunogold labeling and electron microscopy. The subcellular localization of vegetative ${\beta}$-expansins has not yet been studied. Using antibodies specific for OsEXPB3, a vegetative ${\beta}$-expansin of rice (Oryza sativa L.), we found that OsEXPB3 is tightly bound to the cell wall and, unlike ${\alpha}$-expansins, cannot be solubilized with extraction buffer containing 1 M NaCl. OsEXPB3 protein could only be extracted with buffer containing SDS. The subcellular localization of the OsEXPB3 protein was confirmed by immunogold labeling and electron microscopy. Gold particles were mainly distributed over the primary cell walls. Immunohistochemistry showed that OsEXPB3 is present in all regions of the coleoptile and root tissues tested.

A Study on Buffer Processing using Push Out Scheme with Variable Threshold (가변 임계값을 갖는 푸쉬 아웃 기법을 이용한 트래픽 제어)

  • 최인수;박호균;류황빈
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.18 no.12
    • /
    • pp.1884-1892
    • /
    • 1993
  • In push out scheme, high priority cell which arrives when the buffer is full pushs low priority cell. The PBS scheme provides priority by variable threshold in buffer.In this paper, for Controlling congestion in ATM network we propose buffer processing method in which the PBS scheme has variable threshold. And we analysis The performance of this scheme. As a result of simulation, the proposed push out scheme with variable threshold reduces the loss of low priority cell compared with existing push out scheme. This proposed method not only reduces the loss of high priority cell like existing push out scheme but also reduces the loss of low priority cell by variable threshold.

  • PDF

Multiplexing Structure and Buffer Control in an ATM Switching System (ATM스위치 시스템의 다중화 구조 및 버퍼 제어)

  • 최성호
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.2 no.2
    • /
    • pp.181-186
    • /
    • 1998
  • This paper presents multiplexing structures to provide various subscriber interfaces in an ATM switching system with a high speed internal link, and analyzes the schemes in terms of a mean cell delay and a buffer sin. And we proposed a buffer management strategy to minimize a cell loss and accommodate new ATM transfer capabilities.

  • PDF

Thermal Aware Buffer Insertion in the Early Stage of Physical Designs

  • Kim, Jaehwan;Ahn, Byung-Gyu;Kim, Minbeom;Chong, Jongwha
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.12 no.4
    • /
    • pp.397-404
    • /
    • 2012
  • Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.

Design of a shared buffer memory switch with a linked-list architecture for ATM applications (Linked-list 구조를 갖는 ATM용 공통 버퍼형 메모리 스위치 설계)

  • 이명희;조경록
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.21 no.11
    • /
    • pp.2850-2861
    • /
    • 1996
  • This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.

  • PDF

Characterization of Chemical Bath Deposited ZnS Thin Films and Its application to $Cu(InGa)Se_2$ Solar Cells (용액성장법에 의한 황화아연 박막층 분석 및 이의 CIGS 태양전지로의 응용)

  • Shin, Dong-Hyeop;Larina, Liudmila;Yun, Jae-Ho;Ahn, Byung-Tae
    • 한국신재생에너지학회:학술대회논문집
    • /
    • 2009.06a
    • /
    • pp.138-138
    • /
    • 2009
  • Recently, thin-film solar cells of Cu(In,Ga)$Se_2$(CIGS) have reached a high level of performance, which has resulted in a 19.9%-efficient device. These conventional devices were typically fabricated using chemical bath deposited CdS buffer layer between the CIGS absorber layer and ZnO window layer. However, the short wavelength response of CIGS solar cell is limited by narrow CdS band gap of about 2.42 eV. Taking into consideration the environmental aspect, the toxic Cd element should be replaced by a different material. It is why during last decades many efforts have been provided to achieve high efficiency Cd-free CIGS solar cells. In order to alternate CdS buffer layer, ZnS buffer layer is grown by using chemical bath deposition(CBD) technique. The thickness and chemical composition of ZnS buffer layer can be conveniently by varying the CBD processing parameters. The processing parameters were optimized to match band gap of ZnS films to the solar spectrum and exclude the creation of morphology defects. Optimized ZnS buffer layer showed higher optical transmittance than conventional thick-CdS buffer layer at the short wavelength below ~520 nm. Then, chemically deposited ZnS buffer layer was applied to CIGS solar cell as a alternative for the standard CdS/CIGS device configuration. This CIGS solar cells were characterized by current-voltage and quantum efficiency measurement.

  • PDF

A simulation of high efficiently thin film solar cell with buffer layer (버퍼층 삽입을 통한 박막 태양전지의 고효율화 시뮬레이션)

  • Kim, Heejung;Jang, Juyeon;Baek, Seungsin;Yi, Junsin
    • 한국신재생에너지학회:학술대회논문집
    • /
    • 2011.11a
    • /
    • pp.64.2-64.2
    • /
    • 2011
  • a-Si 박막 태양전지는 a-Si:H을 유리 기판 사이에 주입해 만드는 태양전지로, 뛰어난 적용성과 경제성을 지녔으나 c-Si 태양전지에 비해 낮은 변환 효율을 보이는 단점이 있다. 변환 효율을 높이기 위한 연구 방법으로는 a-Si 박막 태양전지 단일cell 제작 시 high Bandgap을 가지는 p-layer를 사용함으로 높은 Voc와 Jsc의 향상에 기여할 수 있는데, 이 때 p-layer의 defect 증가와 activation energy 증가도 동시에 일어나 변환 효율의 증가폭을 감소시킨다. 이를 보완하기 위해 본 실험에서는 p-layer에 기존의 p-a-Si:H를 사용함과 동시에 high Bandgap의 buffer layer를 p-layer와 i-layer 사이에 삽입함으로써 그 장점을 유지하고 높은 defect과 낮은 activation energy의 영향을 최소화하였다. ASA 시뮬레이션을 통해 a-Si:H보다 high Bandgap을 가지는 a-SiOx 박막을 사용하여 p-type buffer layer의 두께를 2nm, Bandgap 2.0eV, activation energy를 0.55eV로 설정하고, i-type buffer layer의 두께를 2nm, Bandgap 1.8eV로 설정하여 삽입하였을 때 박막 태양전지의 변환 효율 10.74%를 달성할 수 있었다. (Voc=904mV, Jsc=$17.48mA/cm^2$, FF=67.97).

  • PDF

Effect of the LDC Buffer Layer in LSGM-based Anode-supported SOFCs (LSGM계 음극지지형 고체산화물 연료전지에 적용된 LDC 완충층의 효과)

  • Song, Eun-Hwa;Chung, Tai-Joo;Kim, Hae-Ryoung;Son, Ji-Won;Kim, Byung-Kook;Lee, Jong-Ho;Lee, Hae-Weon
    • Journal of the Korean Ceramic Society
    • /
    • v.44 no.12
    • /
    • pp.710-714
    • /
    • 2007
  • LSGM$(La_{0.8}Sr_{0.2}Ga_{0.8}Mg_{0.2}O_{3-{\delta}})$ is the very promising electrolyte material for lower-temperature operation of SOFCs, especially when realized in anode-supported cells. But it is notorious for reacting with other cell components and resulting in the highly resistive reaction phases detrimental to cell performance. LDC$(La_{0.4}Ce_{0.6}O_{1.8})$, which is known to keep the interfacial stability between LSGM electrolyte and anode, was adopted in the anode-supported cell, and its effect on the interfacial reactivity and electrochemical performance of the cell was investigated. No severe interfacial reaction and corresponding resistive secondary phase was found in the cell with LDC buffer layer, and this is due to its ability to sustain the La chemical potential in LSGM. The cell exhibited the open circuit voltage of 0.64V, the maximum power density of 223 $mW/cm^2$, and the ohmic resistance of $0.17{\Omega}cm^2$ at $700^{\circ}C$. These values were much improved compared with those from the cell without any buffer layer, which implies that formation of the resistive reaction phases in LSGM and then deterioration of the cell performance is resulted mainly from the La diffusion from LSGM electrolyte to anode.

Approximate Cell Loss Performance in ATM Networks: In Comparison with Exact Results

  • Lee, Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.25 no.4A
    • /
    • pp.489-495
    • /
    • 2000
  • In this paper we propose an approximate method to estimate the cell loss probability(CLP) due to buffer overflow in ATM networks. The main idea is to relate the buffer capacity with the CLP target in explicit formula by using the approximate upper bound for the tail distribution of a queue. The significance of the proposition lies in the fact that we can obtain the expected CLP by using only the source traffic data represented by mean rate and its variance. To that purpose we consider the problem of estimating the cell loss measures form the statistical viewpoint such that the probability of cell loss due to buffer overflow does not exceed a target value. In obtaining the exact solution we use a typical matrix analytic method for GI/D/1B queue where B is the queue size. Finally, in order to investigate the accuracy of the result, we present both the approximate and exact results of the numerical computation and give some discussion.

  • PDF