• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.461-464
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• 1999

This study has been investigated that traps generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The charge state of the traps can easily be changed by application of low voltages after the stress high voltage. These trap generation involve either electron impact ionization processes or high field generation processes. It determined to the relative traps locations inside the oxides ranges from 113.4$\AA$ to 814$\AA$ with capacitor areas of 10$^{-3}$ $\textrm{cm}^2$ . The oxide charge state of traps generated by the stress high voltage contain either a positive or a negative charge.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.2
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• pp.17-24
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform new both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of 1011~1021[states/eV/cm2] after a stress voltage. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.43-46
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of $10^{11}\sim10^{21}$[states/eV/$cm^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}\sim10^{13}$[states/eV/$cm^2$]. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.6
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• pp.412-417
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• 2000

High electric field stressed trap distributions were investigated in the thin silicon oxide of polycrystalline silicon gate metal oxide semiconductor capacitors. The transient currents associated with the off time of stressed voltage were used to measure the density and distribution of high voltage stress induced traps. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface in polycrystalline silicon gate metal oxide semiconductor devices. The stress generated trap distributions were relatively uniform the order of $10^{11}$~$10^{12}$ [states/eV/$\textrm{cm}^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}$~$10^{13}$ [states/eV/$\textrm{cm}^2$]. It was appeared that the transient current that flowed when the stress voltages were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Transactions of the Korean hydrogen and new energy society
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• v.27 no.2
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• pp.155-162
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• 2016

A proton exchange membrane fuel cell (PEMFC) produces only water at cathode by an electrochemical reaction between hydrogen and oxygen. The generated water is transported across the membrane from the cathode to the anode. The transported water collected in water-trap and drained to the cathode within the humidifier outlet. If the condensate water is not being drained at the appropriate time, condensate water in the anode can cause the performance degradation or fuel efficiency degradation of fuel cell by the anode flooding or unnecessary hydrogen discharge. In this study, we proposed an optimization method of condensate water drain logic for the water drain performance and the water drain algorithm as considered the condensate water generating speed prep emergency case. In conclusion, we developed the water management strategy of fuel processing system (FPS) as securing fuel efficiency and operating stability.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.17-20
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• 2002

This study has been investigated that traps generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The charge state of the traps can easily be changed by application of low voltages after the stress high voltage. These trap generation involve either electron impact ionization processes or high field generation processes. It determined to the relative traps locations inside the oxides ranges from 113.4A to 814A with capacitor areas of 10$^{-3}$ $\textrm{cm}^2$ The oxide charge state of traps generated by the stress high voltage contain either a positive or negative charge.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.9 no.5
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• pp.521-526
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• 1999

It was investigated that traps were generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The charge state of the traps can easily be changed by application of low voltage after the stress high voltage. It determined to the relative traps locations inside the oxides ranges from 113.4$\AA$to 814$\AA$ with capacitor areas of $10^{-3}{$\mid$textrm}{cm}^2$. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The oxide charge state of traps generated by the stress high voltage contain either a positive or a negative charge.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.1014-1018
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• 2007

We have demonstrated the enhancement of the power efficiency and device lifetime of organic light-emitting diodes (OLEDs) by introducing the ETL 1 / ETL2 (composite ETL) structure between EML and cathode and the HIL1 (composite HIL) / HIL2 between anode and HTL. Compared to reference devices retaining conventional architecture, novel OLED structure shows an outstanding EL efficiency that is 1.6 times higher (${\sim}4.5$ lm/w versus ${\sim}$ 2.71 lm/w for the reference device) and lower driving voltage $({\bigtriangleup}V>1V)$, but also a longer lifetime and smaller operating voltage drift over time. It is suggested in this work that the device performance can be improved by in-situ ohmic contact through novel electron controlled structure and reduction of charge accumulation in the interface through composite HIL

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.9
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• pp.502-509
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• 2000

In this paper in order to evaluat quantitavely the formation mechanism of space charge and its effects on the conduction characteristics in LDPE we have carried out the numerical analysis on the basis of experimental results of space charge distribution cathode field and current with time which had been simultaneously measured at applied field of 50kV/mm and room temperature. As the models for numerical analysis we employ the Richarson-Schottky theory for charge injection from electrode into LDPE and the band-tail conduction at crystalline regions and the hopping conduction by traps which mainly exist at the interface regions of crystalline-amorphous region for charge transport in LDPE. Futhermore in order to investigate the influence of physical parameters on the time characteristcs of space charge distribution and measured current we have changed the values of trap density activation energies for charge injection and transport and have analyzed their effects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.177-180
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• 2004

발광층에 Alq3와 rubrene을 mixed host로 사용하고 DCJTB를 형광 dopant로 사용한 다층 박막 구조의 red OLEDs를 제작하였다. 소자의 구조는 $ITO:Anode(120nm)/{\alpha}-NPD:HTL(40nm)/Alq_3+Rubrene(mixed\;host\;1:1)+DCJTB(red\;dopant\;3%)+:EML(20nm)/Alq_3:ETL(40nm)/MgAg(Mg\;5%\;wt):Cathode(150nm)$ 로서 EML내부에 DCJTB를 Totally Doping Method와 Dotted-Line Doping Method의 두 가지 방법으로 도핑 하였다. Mixed host구조에 DCJTB를 6구간으로 나누어 Dotted Line Doping한 소자는 luminance yield가 $9.2cd/A@10mA/cm^2$ 이었다. 이 소자는 DCJTB만을 Totally Doping한 소자의 luminance yield $3.2cd/A@10mA/cm^2$에 비해 약 190%정도의 높은 효율 향상을 보였다. 또한 $10mA/cm^2$에 도달하는 전압은 5.5V Vs. 8.5V로서 mixed host를 사용한 소자에서 약 3V정도 구동전압이 낮아지는 효과가 있었다. 발광 스펙트럼의 Full Width Half Maximum(FWHM)은 각각 56.6nm와 61nm로서 rubrene을 mixed host로 사용한 소자에서 높은 색 순도를 얻을 수 있었다. 이러한 성능의 향상은 $Alq_3$와 혼합된 rubrene에 의한 낮은 전하주 입장벽, 높은 전류밀도에서 나타나는 발광감쇄현상의 감소, 그리고 발광층의 DLD구조에 의한 전하의 trap & confinement 에 따른 발광 exciton의 형성확률이 증가한데서 나타났다고 생각된다.