• Journal of Power Electronics
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• 제14권3호
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• pp.507-518
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• 2014

This paper presents a new cascaded asymmetrical single phase multilevel converter with a lower number of power semiconductor switches and isolated DC sources. Therefore, the number of power electronic devices, converter losses, size, and cost are reduced. The proposed multilevel converter topology consists of two H-bridges connected in cascaded configuration. One H-bridge operates at a high frequency (high frequency inverter) and is capable of developing a two level output while the other H-bridge operates at the fundamental frequency (low frequency inverter) and is capable of developing a multilevel output. The addition of each power electronic switch to the low frequency inverter increases the number of levels by four. This paper also introduces a hybrid switching algorithm which uses very simple arithmetic and logical operations. The simplified hybrid switching algorithm is generalized for any number of levels. The proposed simplified switching algorithm is developed using a TMS320F2812 DSP board. The operation and performance of the proposed multilevel converter are verified by simulations using MATLAB/SIMULINK and experimental results.

• 전기학회논문지
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• 제64권5호
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• pp.718-725
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• 2015

This paper proposes a novel level-shifted PWM (LS-PWM) strategy for fault tolerant cascaded multilevel inverter. Most proposed fault-tolerant operation methods in many of studies are based on a phase-shifted PWM (PS-PWM) method. To apply these methods to multilevel inverter systems using LS-PWM, two additional steps will be implemented. During the occurrence of a single-inverter-cell fault, the carrier bands scheme is reconfigured and modulation levels of inverter cells are reassigned in this proposed fault-tolerant operation. The proposed strategy performs balanced three-phase line-to-line voltages and line currents when a switching device fault occurs in a cascaded multilevel inverter using LS-PWM. Simulation and experimental results are included in the paper to verify the proposed method.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2005년도 전기학술대회논문집
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• pp.1022-1028
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• 2005

This paper is presented the analysis results and simulation results of cascaded H-bridge 7 level inverter with various modulation index. Stepped waveform having number of switching was used to eliminate harmonic components. Switching angles according to modulation index are calculated numerically. Therefore, 3 times of switching with 7 level topology and QWS(Quarter Wave Symmetry) could eliminate 5th and 7th harmonics. The harmonic characteristics are compared to those of space vector modulation method which known as common modulation method in industrial field. Stepped waveform method showed higher ability to reduce, especially lower order of harmonics.

• Journal of Power Electronics
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• 제16권6호
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• pp.2067-2075
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• 2016

Cascaded H-bridge multilevel inverters are currently used because it enables the integration of various sources, such as batteries, ultracapacitors, photovoltaic array and fuel cells in a single system. Conventional modulation schemes for multilevel inverters have concentrated mainly on the generation of a low harmonic output voltage, which results in less effective utilization of connected sources. Less effective utilization leads to a difference in the charging/discharging of sources, causing unsteady voltages over a long period of operation and a reduction in the lifetime of the sources. Hence, a charge balance control scheme has to be incorporated along with the modulation scheme to overcome these issues. In this paper, a new approach for charge balancing in symmetric cascaded H-bridge multilevel inverter that enables almost 100% charge balancing of sources is presented. The proposed method achieves charge balancing without any additional stages or complex circuit or considerable computational requirement. The validity of the proposed method is verified through simulation and experiments.

• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.270-279
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• 2018

This paper elucidates a hysteresis current controller for enhancing the performance of static synchronous compensator (STATCOM) using cascaded H-bridge multilevel inverter. Due to the rising power demand and growing conventional generation costs a new alternative in renewable energy source is gaining popularity and recognition. A five level single phase cascaded multilevel inverter with two separated dc sources, which is energized by photovoltaic - wind hybrid energy source. The voltages across the each dc source is balanced and standardized by the proposed hysteresis current controller. The performance of STATCOM is analyzed by connecting with grid connected system, under the steady state & dynamic state. To reduce the Total Harmonic Distortion (THD) and to improve the output voltage, closed loop hysteresis current control is achieved using PLL and PI controller. The performance of the proposed system is scrutinized through various simulation results using matlab/simulink and hardware results are also verified with simulation results.

• 전력전자학회논문지
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• 제19권2호
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• pp.157-163
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• 2014

This paper proposes a two-stage step-down buck and a tapped-inductor boost cascaded converter for high efficiency photovoltaic micro-inverter applications. The proposed inverter is a new structure to inject a rectified sinusoidal current into a low-frequency switching inverter for single-phase grid with unity power factor. To build a rectified-waveform of the output current. the converter employs both of a high efficiency step-up and a step-down converter in cascade. In step-down mode, tapped inductor(TI) boost converter stops and the buck converter operates alone. In boost mode, the TI converter operates with the halt of buck operation. The converter provides a rectified current to low frequency inverter, then the inverter converts the current into a unity power-factor sinusoidal waveform. By applying a TI, the converter can decrease the turn-on ratios of the main switch in TI boost converter even with an extreme step-up operation. The performance validation of the proposed design is confirmed by an experimental results of a 120W hardware prototype.

• Journal of Power Electronics
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• 제18권2호
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• pp.522-532
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• 2018

The cascaded H Bridge (CHB) multilevel inverter (MLI) is popular among the classical MLI topologies due to its modularity and reliability. Although space vector modulation (SVM) is the most suitable modulation scheme for MLIs, it has not been used widely in industry due to the higher complexity involved in its implementation. In this paper, a simple and novel generalized SVM algorithm is proposed, which has both reduced time and space complexity. The proposed SVM involves the generalization of both the duty cycle calculation and switching sequence generation for any n-level inverter. In order to generate the gate pulses for an inverter, a generalized switch matrix (SM) for the CHB inverter is also introduced, which further simplifies the algorithm. The algorithm is tested and verified for three-phase, three-level and five-level CHB inverters in simulations and hardware implementation. A comparison of the proposed method with existing SVM schemes shows the superiority of the proposed scheme.

• Journal of Power Electronics
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• 제18권1호
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• pp.56-69
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• 2018

In this paper, an improved Space Vector Modulation (SVM) based fault tolerant operation on a nine-level Cascaded H-Bridge (CHB) inverter with an additional backup circuit is proposed. Any type of fault in a power converter may result in a power interruption and productivity loss. Three different faults on H-bridge modules in all three phases based on the SVM approach are investigated with diagrams. Any fault in an inverter phase creates an unbalanced output voltage, which can lead to instability in the system. An additional auxiliary unit is connected in series to the three phase cascaded H-bridge circuit. With the help of this and the redundant switching states in SVM, the CHB inverter produces a balanced output with low harmonic distortion. This ensures high DC bus utilization under numerous fault conditions in three phases, which improves the system reliability. Simulation results are presented on three phase nine-level inverter with the automatic fault detection algorithm in the MATLAB/SIMULINK software tool, and experimental results are presented with DSP on five-level inverter to validate the practicality of the proposed SVM fault tolerance strategy on a CHB inverter with an auxiliary circuit.

• Journal of international Conference on Electrical Machines and Systems
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• 제2권2호
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• pp.190-196
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• 2013

It presents a unification of buck-boost and flyback converter for driving a cascaded H-bridge multilevel inverter with a single independent DC voltage source. Cascaded H-bridge multilevel inverter is useful to make many output voltage levels for sinusoidal waveform by combining two or more H-bridge modules. However, each H-bridge module needs an independent DC voltage source to generate multi levels in an output voltage. This topological characteristic brings a demerit of increasing the number of independent DC voltage sources when it needs to increase the number of output voltage levels. To solve this problem, we propose a converter combining a buck-boost converter with a flyback converter. The proposed converter provides independent DC voltage sources at back-end two H-bridge modules. After analyzing theoretical operation of the circuit topology, the validity of the proposed approach is verified by computer-aided simulations using PSIM and experiments.

• Transactions on Electrical and Electronic Materials
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• 제18권4호
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• pp.229-236
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• 2017

This paper deals with the design and implementation of an efficient topology for cascaded multilevel inverters with reduced part counts. In the proposed design, a well-established basic unit is first developed. The series extension of this unit results in the formation of the proposed multilevel inverter. The proposed design minimizes the number of power electronic components including insulated-gate bipolar transistors and gate driver circuits, which in turn cuts down the size of the inverter assembly and reduces the operating power losses. An explicit control strategy with enhanced device efficiency is also acquired. Thus, the part count reductions enhance not only the economical merits but also the technical features of the entire system. In order to accomplish the desired operational aspects, three algorithms are considered to determine the magnitudes of the dc voltage sources effectively. The proposed topology is compared with the conventional cascaded H-bridge multilevel inverter topology, to reflect the merits of the presented structure. In continue, both the analytical and experimental results of a cascaded 31-level structure are analyzed. The obtained results are discussed in depth, and the exemplary performance of the proposed structure is corroborated.