• Title/Summary/Keyword: Carrier state

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General Idea of NGH and NGH Carrier (NGH 특성 및 NGH 수송선 개요)

  • Kang, Gon;Lee, Sang-Su;Kim, Jung-Hoon
    • Proceedings of the Korean Society of Marine Engineers Conference
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    • 2011.06a
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    • pp.13-14
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    • 2011
  • Methane Hydrates or Natural Gas Hydrates (hereinafter NGH) are solid-state energy source formed by the clathration of methane gas in water molecules at low temperature and high pressure. NGH is also known as "burning ice" because of its burning property and appearance similar to that of dry ice. Today, concerns about the NGH are rising as an environment-friendly energy source that can replace fossil fuels. In this paper, to keep pace with the research and development of the NGH, the properties of the NGH and the general features of NGH carriers are introduced.

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Hot-Carrier-Induced Degradation in Submicron MOS Transistors (Submicron MOS 트랜지스터의 뜨거운 운반자에 의한 노쇠현상)

  • 최병진;강광남
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.7
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    • pp.780-790
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    • 1988
  • We have studied the hot-carrier-induced degradation caused by the high channel electric field due to the decrease of the gate length of MOSFET used in VLSI. Under DC stress, the condition in which maximum substrate current occures gave the worst degradation. Under AC dynamic stress, other conditions, the pulse shape and the falling rate, gave enormous effects on the degradation phenomena, especially at 77K. Threshold voltage, transconductance, channel conductance and gate current were measured and compared under various stress conditions. The threshold voltage was almost completely recovered by hot-injection stress as a reverse-stress. But, the transconductance was rapidly degraded under hot-hole injection and recovered by sequential hot-electron stress. The Si-SiO2 interface state density was analyzed by a charge pumping technique and the charge pumping current showed the same trend as the threshold voltage shift in degradation process.

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Charge Pumping Method를 이용한 N-type MOSFET의 Interface Trap(Dit) 분석

  • Go, Seon-Uk;Kim, Sang-Seop;Choe, Byeong-Deok
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.328.1-328.1
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    • 2014
  • MOSFET degradation의 대부분은 hot-carrier injection에 의한 interface state (Dit)의 생성에서 비롯되며 따라서 본 연구에서는 신뢰성에 대한 한 가지 방법으로 Charge pumping method를 이용하여 MOSFET의 interface trap(Dit)의 변화를 측정하였다. 소스와 드레인을 ground로 묶고 게이트에 펄스를 인가한 후 Icp를 측정하여 Dit를 추출하였다. 온도를 293~343 K까지 5 K씩 가변했을 때 293K의 Icp(${\mu}A$)는 0.12 nA 313 K는 0.112 nA 343 K는 0.926 nA이며 Dit (cm-1/eV-1)는 $1.61{\times}10^{12}$ (Cm-2/eV-1) $1.49{\times}10^{12}$ (Cm-2/eV-1) $1.23{\times}10^{12}$ (Cm-2/eV-1)이다. 측정결과 Dit는 Icp가 높은 지점에서 추출되며 온도가 높아지게 되면 Icp전류가 낮아지고 Dit가 줄어드는 것을 볼 수 있다. 온도가 올라가게 되면 carrier들이 trap 준위에서 conduction band 위쪽에 이동하게 되어서 interface에 trap되는 양이 작아지게 된다. 그래서 이때 Icp를 이용해 추출한 Dit 는 실제로 trap의 양이 줄어든 것이 아니라 Thermal excess 현상으로 인해 측정되는 Icp의 양이 줄어든 것으로 분석할 수 있다.

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A Carrier-Rotation Strategy for Voltage Balancing of Flying Capacitors in Flying Capacitor Multi-level Inverter (플라잉 커패시터 멀티-레벨 인버터의 플라잉 커패시터 전압 균형을 위한 캐리어 로테이션 기법)

  • Lee W.K.;Kang D.W;Kim T.J.;Hyun D.S.
    • Proceedings of the KIPE Conference
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    • 2003.07b
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    • pp.630-634
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    • 2003
  • This paper proposes a Carrier-Rotation PWM technique that is new solution for the voltage unbalancing problem of flying capacitors in the Flying Capacitor Multi-level Inverter (FCMI).The proposed PWM technique equalizes the utilization of phase leg voltage redundancies corresponding to the charging and the discharging state of flying capacitors during one switching period of all the switches. it also has the same switch utilization and the reduced harmonics of output voltage. Hence, it is more suitable for the FCMI compared with the conventional solutions. Experimental results on the laboratory prototype flying capacitor 3-level inverter confirm the validity of the proposed PWM technique.

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Gate-tunable Supercurrent in Graphene-based Josephson Junction (그래핀 조셉슨 접합에서 초전류의 게이트 전압 의존성)

  • Jeong, D.;Lee, G.H.;Doh, Y.J.;Lee, H.J.
    • Progress in Superconductivity
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    • v.13 no.1
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    • pp.47-51
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    • 2011
  • Mono-atomic-layer graphene is an interesting system for studying the relativistic carrier transport arising from a linear energy-momentum dispersion relation. An easy control of the carrier density in graphene by applying an external gate field makes the system even more useful. In this study, we measured the Josephson current in a device consisting of mono-layer graphene sheet sandwiched between two closely spaced (~300 nm) aluminum superconducting electrodes. Gate dependence of the supercurrent in graphene Josephson junction follows the gate dependence of the normal-state conductance. The gate-tunable and relatively large supercurrent in a graphene Josephson junction would facilitate our understanding on the weak-link behavior in a superconducting-normal metal-superconducting (SNS) type Josephson junction.

The improvement of the operation for lcl international transportation (LCL 화물의 국제 해상운송 운영 개선 방안 제시)

  • Lee, Gil-Hwan;Gang, Gyeong-Sik
    • Proceedings of the Safety Management and Science Conference
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    • 2012.04a
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    • pp.371-380
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    • 2012
  • Although all costs concerned in transportation be separated by region and each terms and conditions of Incoterms that state cleary them who have to pay the charges. But, almost lcl exporters donot want to pay their charges the carriers at loading port eventhough they make the contracts with the importer as FOB and CFR of Incoterms. And the carrier have been do not bill the FOB charges to the shipper. Now, there are no more Incoterms in LCL transportation. So, the importer have been payed loading port charges twice, first, the contract with the shipper, secondly, through the destination charge. These problems make decreasing of trading volume and increasing of logistics costs. We suggest every traders and carriers separate the costs as per the price terms and conditions of incoterms and bill/receive the costs separated the trader who have to pay the charges as per their price terms. It will bring mutual success in the world and increasing trade.

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Study on Improved Switching Characteristics of LIGBT by the Trap Injection (Trap 주입에 의한 LIGBT의 스위칭 특성 향상에 관한 연구)

  • 추교혁;강이구;성만영
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.2
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    • pp.120-124
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    • 2000
  • In this paper, the effects of trap distribution on switching characteristis of a lateral insulated gate bipolar transistor (LIGBT) are investigated. The simulations are performed in order to to analyze the effect of the positon, width and concentration of trap distribution model with a reduced minority carrier lifetime using 2D device simulator MEDICI. The turn off time for the proposed LIGBT model A with the trap injection is 0.8$mutextrm{s}$. These results indicate the improvement of about 2 times compared with the conventional LIGBT. It is shown that the trap distribution model is very effective to reduce the turn-off time with a little increasing of on-state voltage drop.

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Properties for the Behavior of Charged Carrier within the Intergranular Layer of ZnO Varistor Fabricated 3-Composition Seed Grain Method (3-성분 종입자 법으로 제조한 ZnO 바리스터의 입계모델에서 캐리어의 거동 특성)

  • Jang, Kyung-Uk;Lee, Joon-Ung
    • Proceedings of the KIEE Conference
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    • 1993.07b
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    • pp.1159-1161
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    • 1993
  • This paper may be presented the carrier oscillation properties for the varistor fabricated by a new method of three-composition seed grain, in order to analyze the behavior of carriers at the its equivalent circuit model. The oscillation phenomena of carriers appeared from current-voltage characteristics under knee voltage is shown by the transient flow of non trapped carriers group in the trap level of intergranular layer, surface state and/or depletion layer. However, Current oscillation phenomena is hardly shown in the high electric field. The injected carriers from both electrodes are directly flowed from the conduction band of forward biased grain through the intergranular layer into the reverse biased grain, because the trap level in the electric field above the knee voltage is mostly filled.

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Effect of Alternate Bias Stress on p-channel poly-Si TFT`s (P-채널 다결정 실리콘 박막 트랜지스터의 Alternate Bias 스트레스 효과)

  • 김영호;조봉희;강동헌;길상근;임석범;임동준
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.14 no.11
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    • pp.869-873
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    • 2001
  • The effects of alternate bias stress on p-channel poly-Si TFT\`s has been systematically investigated. We alternately applied positive and negative bias stress on p-channel poly-Si TFT\`s, device Performance(V$\_$th/, g$\_$m/, leakage current, S-slope) are alternately appeared to be increasing and decreasing. It has been shown that device performance degrade under the negative bias stress while improve under the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ interface under alternate bias stress.

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Non-iterative Bit Loading Algorithm for OFDM in Independent and Correlated fading

  • Manry, John W.;Nagaraj, Santosh
    • Journal of Information Processing Systems
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    • v.10 no.2
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    • pp.163-175
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    • 2014
  • This paper will focus on improving the performance of orthogonal frequency division multiplexing (OFDM) in Rayleigh fading environments. The proposed technique will use a previously published method that has been shown to improve OFDM performance in independent fading, based on ordered sub-carrier selection. Then, a simple non-iterative method for finding the optimal bit-loading allocation was proposed. It was also based on ordered sub-carrier selection. We compared both of these algorithms to an optimal bit-loading solution to determine their effectiveness in a correlated fading environment. The correlated fading was simulated using the JTC channel models. Our intent was not to create an optimal solution, but to create a low complexity solution that can be used in a wireless environment in which the channel conditions change rapidly and that require a simple algorithm for fast bit loading.