• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.606-610
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• 2003

This paper presents a simple carrier symmetric method for the voltage balance of flying capacitors in FCMLI(flying capacitor multi-level inverter). To achieve the voltage balance of flying capacitors, the utilization of each carrier must be balanced during a half-cycle of the switching period such as PSPWM(Phase-Shifted PWM). However, the CRPWM(Carrier Redistribution PWM) method causes the fluctuation of flying capacitor voltages because the balanced utilization of carriers is not achieved. Moreover, it does not consider that the load current change has an influence on flying capacitor voltages by assuming that the current flows Into the load. To overcome the drawbacks of CRPWM, it is modified by the technique that carriers of each band are disposed symmetrically at every fundamental period. Firstly, the CRPWN method is reviewed and the theory on voltage balance of flying capacitors is analyzed. The proposed method Is introduced and is verified through the experiment result.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.277-284
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• 2017

For passive power factor correction, the valley fill circuit approach is attractive for low power applications because of low cost, high efficiency, and simple circuit design. However, to vouch for the product quality, two dc-link capacitors in the valley fill circuit should be selected to withstand the peak rectified ac input voltage. The common mode (CM) and differential mode (DM) choke should be used to suppress the electromagnetic interference (EMI) noise, thereby resulting in large size volume product. This paper presents the practical design and implementation of a valley fill flyback converter with reduced dc link capacitors and EMI magnetic volumes. By using the proposed over voltage protection circuit, dc-link capacitors in the valley fill circuit can be selected to withstand half the peak rectified ac input voltage, and the proposed CM/DM choke can be successfully adopted. The proposed circuit effectiveness is shown by simulation and experimentally verified by a 78W prototype.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.369-372
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• 2017

This paper presents a control scheme for three-level NPC inverters using small DC-link capacitors. To reduce the inverter system volume, the film capacitor with small capacitance is a promising candidate for the DC-link. When small capacitors are applied in a three level inverter, however, the AC ripple component increases in the DC-link NPV (neutral point voltage). In addition, the three-phase input grid currents are distorted when the DC-link capacitors are fed by diode rectifier. In this paper, the additional circuit is applied to compensate for small capacitor systems defect, and the offset voltage injection method is presented for the stabilization in NPV. These two proposed processes evidently ensure the quality improvement of the input grid currents and output load currents. The feasibility of the proposed method is verified by experimental results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.10
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• pp.25-32
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• 2000

We provided a model for accurately computing the Hysteresis characteristics of the ferrelectric thin film capacitors. This model is developed form the semi-empirical ferroelectric model based on the double well harmonic oscillator. We have seen that this model is consistent with physical analysis using the Preisach's hysteresis distribution. This model includes the parameters representing the slope of changing Hysteresis curves and the imprint of ferroelectric capacitors. Besides, we showed that this model could predict accurate sub-hystersis loop by the turning points when the polarities of applied voltage were changed before saturation. The simulation and measurement result showed that this model is well applicable to both PZT and SBT materials. This model has been described by AHDL and successfully implemented into Spectre simulator to provide circuit design environment of commercial CAD tools such as Cadence software.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.298-301
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• 2005

The flying capacitor voltage control of the flying capacitor multi-level inverter (FCMLI) is very important for safe operation. The voltage unbalancing of flying capacitors caused serious problems in safety and reliability of system. In the FCMLI, balancing problem of the flying capacitor has its applications limited. The voltage unbalance is occurred by the difference of each capacitors charging and discharging time applied to FCMLI. This paper investigates and analyzes multi-carrier PWM methods to solve capacitor voltage balancing problem. The Phase-Shift PWM (PSPWM) method that is commonly used, The Modified Carrier-Redistribution PWM (MCRPWM) method and The Saw-Tooth-Rotation PWM (STRPWM) method are discussed and compared with respect to switching state, balancing voltage of capacitors and output waveform. These three PWM methods are analyzed by using a flying capacitor three-level inverter and provided result through simulation. Finally, the harmonics about the output voltages of their methods are compared using the harmonic distortion factor (HDF).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.329-332
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• 1999

In this paper, BST((Bao.&o,dTi0:3) thin films were deposited by the rf magnetron sputtering method on Pt/$SiO_2$/Si substrate. Pt, $RuO_2$, Ag, Cu films for the formation of top electrode were deposited on BST thm films. And then Top Electrodes/BST/Pt capacitors were annealed with rapid thermal annealing(RTA) at various temperature. We have investigated effect of post-annealing on the electrical properties such as dielectric constant and leakage current of the capacitors. It was found that electrical properties of the capacitors were greatly depended on the annealing temperatures as well as the materials of top electrodes. In BST thin films with Pt top electrode was annealed at $700^{\circ}C$. the dielectric constant was measured to the value of 346 at l[kHzl and the leakage current was obtained to the value of $8.76\times10^8$[A/$\textrm{cm}^2$] at the forward bias of 2[V].

• Transactions on Electrical and Electronic Materials
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• v.5 no.1
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• pp.19-23
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• 2004

A novel method of high speed, accurate circuit simulation in 3-dimensional (3-D) parallel-plate capacitors is investigated. The basic concept of the circuit simulation methods is partial element equivalent circuit model. The three test structures of 3-D parallel-plate capacitors are fabricated by using multi-layer low-temperature co-fired ceramic (LTCC) process and their S-parameters are measured between 50 MHz and 5 GHz. S-parameters are converted to Y-parameters, for comparing measured data with simulated data. The circuit model parameters of the each building block are optimized and extracted using HSPICE circuit simulator. This method is convenient and accurate so that circuit design applications can be easily manipulated.

• Journal of Power Electronics
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• v.15 no.1
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• pp.31-38
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• 2015

In this paper, a buck-boost type battery charger is developed for charging battery set with a lower voltage. This battery charger is configured by a rectifier circuit, an integrated boost/buck power converter and a switched capacitors circuit. A boost power converter and a buck power converter sharing a common power electronic switch are integrated to form the integrated boost/buck power converter. By controlling the common power electronic switch, the battery charger performs a hybrid constant-current/constant-voltage charging method and gets a high input power factor. Accordingly, both the power circuit and the control circuit of the developed battery charger are simplified. The switched capacitors circuit is applied to be the output of the boost converter and the input of the buck converter. The switched capacitors circuit can change its voltage according to the utility voltage so as to reduce the step-up voltage gain of the boost converter when the utility voltage is small. Hence, the power efficiency of a buck-boost type battery charger can be improved. Moreover, the step-down voltage gain of the buck power converter is reduced to increase the controllable range of the duty ratio for the common power electronic switch. A prototype is developed and tested to verify the performance of the proposed battery charger.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1587-1588
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• 2006

Tn this paper, PCB (Printed Circuit Board) embedded $BaTiO_3$ MIM capacitors were designed, fabricated, and characterized for low cost organic SOP applications by using 3-D EM simulator and low temperature processes. Size of electrodes and thickness of high dielectric films are optimized for improving the performance characteristics of the proposed embedded MIM capacitors at high frequency regime. The selected thicknesses of the $BaTiO_3$ film are $12{\mu}m$, $16{\mu}m$, and $20{\mu}m$. The fabricated MIM capacitor with dielectric constant of 30 and thickness of $12{\mu}m$ has capacitance density of $21.5p\;F/mm^2$ at 100MHz, maximum quality factor of 37.4 at 300 MHz, a quality factor of 30.9 at 1GHz, self resonant frequency of 5.4 GHz, respectively. The measured capacitances and quality factors are well matched with 3-D EM simulated ones. These embedded capacitors are promising for SOP based advanced electronic systems with various functionality, low cost, small size and volume.

• Proceedings of the KIEE Conference
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• 2007.11a
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• pp.100-101
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• 2007

Polymer thick film capacitors were successfully fabricated by using ink-jet printing and screen printing technology. First, a bottom electrode was patterned by ink-jet printing of a nano-sized silver ink. Next, a dielectric layer was formed by the screen printing, then a top electrode was pattern by ink-jet printing of a nano-sized silver ink. The printed area of the dielectric layers were changed into $2{\times}2m^2$and $4{\times}2m^2$, and also the area of the electrodes were patterned with $1{\times}1mm^2$ and $1{\times}3mm^2$. The thickness of the printed dielectric layer was ranged from 1.1 to $1.4{\mu}m$. The analysis of capacitances verified that the capacitances was proportional to the area of the printed electrode. The capacitances of the fabricated capacitors resulted in one third of the calculated capacitances.