• Applied Chemistry for Engineering
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• v.19 no.4
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• pp.407-412
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• 2008

As an activation procedure, in this study, the oxidation treatment of needle cokes with a dilute nitric acid and sodium chlorate $(NaClO_3)$, combined with heat treatment, was attempted. The structures of acid-treated and pyrolyzed coke were examined with XRD, FESEM, elemental analyzer, BET, and Raman spectroscopy. The behavior of double layer capacitance was investigated with the analysis of charge and discharge. The structure of needle coke treated with acid was revealed to a single phase of (001) diffraction peak after 24 h. On the other hand, thecoke oxidized by heat treatment was reduced to a graphite structure of (002) at $300^{\circ}C$. The distorted graphene layer structure, derived from the process of oxidation and reduction of the inter-layer, makes the pores by the electric field activation at the first charge, and generates the double layer capacitance from the second charge. The cell using pyrolyzed coke with 24 h acid treatment and $300^{\circ}C$ heat treatment exhibited the maximum capacitance per weight and volume of 33 F/g and 30 F/mL at the two-electrode system in the potential range of 0~2.5 V.

• Journal of IKEEE
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• v.13 no.1
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• pp.41-48
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• 2009

This paper describes an implementation of the analog front end (AFE) incorporated with the image signal processing (ISP) unit in the SoC, dominating the performance of the CCD image sensor system. New schemes are exploited in the high-frequency sampling to reduce the sampling uncertainty apparently as the frequency increases, in the structure for the wide-range variable gain amplifier (VGA) capable of $0{\sim}36\;dB$ exponential gain control to meet the needed bandwidth and accuracy by adopting a new parasitic insensitive capacitor array. Moreover, the double cancellation of the black-level noise was efficiently achieved both in the analog and the digital domain. The proposed topology fabricated in a $0.35-{\mu}m$ CMOS process was proved in a full CCD camera system of 10-bit accuracy, dissipating 80 mA at 15 MHz with a 3.3 V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.2
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• pp.135-143
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• 2012

This paper introduces the method to utilize a terminal ground as a radiator only using reactive components without an antenna structure. Characteristics of the proposed antenna is compared with that of the meander IFA on the same ground plane($40{\times}20mm^2$) for the bluetooth band. From simulation and measurement data, it is found that the proposed antenna using only capacitors provides the highest radiation efficiency. This is because of that the higher inductance reduces radiation resistance of a ground and the capacitor has a lower loss resistance comparing to that of the IFA or the inductor. In spite of the high radiation efficiency, the area ($5{\times}2.5mm^2$) of the proposed antenna is less than half of the area ($12{\times}2.5mm^2$) of the IFA.

• Bulletin of the Korean Chemical Society
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• v.35 no.9
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• pp.2630-2634
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• 2014

The surface of natural graphite was modified by the use of hydrogen peroxide and evaluated as an anode material for lithium ion capacitors (LICs). The surface treatment was carried out under various ultrasonic conditions of 200, 300, and 400W, which were applied to a mixture of natural graphite and hydrogen peroxide solution for 1 h. While the bulk structure was maintained, the hexagonal symmetry and physical properties of natural graphite, such as BET surface area, tap density, and particle size, were affected by the surface treatment. FT-IR and XPS measurements confirmed the signature of C=O on the surface of graphite samples after treatment. Both the pristine and surface-treated graphites showed a similar reversible capacity of $370mAhg^{-1}$, and the coulombic efficiency of surface-treated graphite decreased with higher ultrasonic energies (89.1%, 89.0%, and 88.0% for 200, 300, and 400 W) comparing with pristine graphite (89.4%). The capacity retention of LICs was greatly improved with the treated natural graphite. The graphite treated under the ultrasonic energy of 300 W and pristine natural graphite showed capacity retention of 77.5% and 42.9%, implying that the surface treatment was an effective method for the improvement of natural graphite as an anode material for LICs.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.341-350
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• 2016

The current study is dedicated to design a novel coordinated controller to effectively increase power system rotor angle stability. In doing so, the coordinated design of an AVR (automatic voltage regulator), PSS2B, and TCSC (thyristor controlled series capacitor)-based POD (power oscillation damping) controller is proposed. Although the recently employed coordination between a CPSS (conventional power system stabilizer) and a TCSC-based POD controller has been shown to improve power system damping characteristics, neglecting the negative impact of existing high-gain AVR on the damping torque by considering its parameters as given values, may reduce the effectiveness of a CPSS-POD controller. Thus, using a technologically viable stabilizer such as PSS2B rather than the CPSS in a coordinated scheme with an AVR and POD controller can constitute a well-established design with a structure that as a high potential to significantly improve the rotor angle stability. The design procedure is formulated as an optimization problem in which the ITSE (integral of time multiplied squared error) performance index as an objective function is minimized by employing an IPSO (improved particle swarm optimization) algorithm to tune adjustable parameters. The robustness of the coordinated designs is guaranteed by concurrently considering some operating conditions in the optimization process. To evaluate the performance of the proposed controllers, eigenvalue analysis and time domain simulations were performed for different operating points and perturbations simulated on 2A4M (two-area four-machine) power systems in MATLAB/Simulink. The results reveal that surpassing improvement in damping of oscillations is achieved in comparison with the CPSS-TCSC coordination.

• Electrical & Electronic Materials
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• v.16 no.9
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• pp.64.2-65
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• 2003

A 4 nm layer of ZrOx (targeted x-2) was deposited on an interfacial layer(IL) of native oxide (SiO, t∼1.2 nm) surface on 200 mm Si wafers by a manufacturable atomic layer chemical vapor deposition technique at 30$0^{\circ}C$. Some as-deposited layers were subjected to a post-deposition, rapid thermal annealing at $700^{\circ}C$ for 5 min in flowing oxygen at atmospheric pressure. The experimental x-ray diffraction, x-ray photoelectron spectroscopy, high-resolution transmission electron microscopy, and high-resolution parallel electron energy loss spectroscopy results showed that a multiphase and heterogeneous structure evolved, which we call the Zr-O/IL/Si stack. The as-deposited Zr-O layer was amorphous $ZrO_2$-rich Zr silicate containing about 15% by volume of embedded $ZrO_2$ nanocrystals, which transformed to a glass nanoceramic (with over 90% by volume of predominantly tetragonal-$ZrO_2$(t-$ZrO_2$) and monoclinic-$ZrO_2$(m-$ZrO_2$) nanocrystals) upon annealing. The formation of disordered amorphous regions within some of the nanocrystals, as well as crystalline regions with defects, probably gave rise to lattice strains and deformations. The interfacial layer (IL) was partitioned into an upper Si $o_2$-rich Zr silicate and the lower $SiO_{x}$. The latter was sub-toichiometric and the average oxidation state increased from Si0.86$^{＋}$ in $SiO_{0.43}$ (as-deposited) to Si1.32$^{＋}$ in $SiO_{0.66}$ (annealed). This high oxygen deficiency in $SiO_{x}$ indicative of the low mobility of oxidizing specie in the Zr-O layer. The stacks were characterized for their dielectric properties in the Pt/{Zr-O/IL}/Si metal oxide-semiconductor capacitor(MOSCAP) configuration. The measured equivalent oxide thickness (EOT) was not consistent with the calculated EOT using a bilayer model of $ZrO_2$ and $SiO_2$, and the capacitance in accumulation (and therefore, EOT and kZr-O) was frequency dispersive, trends well documented in literature. This behavior is qualitatively explained in terms of the multi-layer nanostructure and nanochemistry that evolves.ves.ves.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.765-770
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• 2001

Metal-ferroelectric-insulator- semiconductor(MFTS) devices by using rapid thermal annealed (RTA) LiNbO$_3$/AIN/Si(100) structures were successfully fabricated and demonstrated nonvolatile memory operations. Metal-insulator-semiconductor(MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2 V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/$\textrm{cm}^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8 V, 50 % duty cycle) in the 500 kHz.

• Journal of Sensor Science and Technology
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• v.27 no.2
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• pp.93-98
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• 2018

In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

• Journal of the Korean Vacuum Society
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• v.5 no.4
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• pp.333-340
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• 1996

The properties of TiN as a barrier against Cu diffusion ere studied by sheet resistance measurement, X-ray diffraction, scanning electron microscopy, Auger electron spectroscopy, and capacitance-voltage(C-V) measurement. The sensitivities of the various methods were compared. Specimens with Cu/TiN/Ti/SiO2/Si structure were prepared by various deposition techniques and annealed at various temperatures ranging from $500^{\circ}C$ to $800^{\circ}C$ in 10%H2/90%Ar ambient for hours. As the effectiveness of the barrier property of TiN against Cu diffusion was vanished, the irregular-shaped sports were observed and outdiffused Si were detected on the surface of the Cu thin film. The C-V characteristics of the MOS capacitors varied drastically with annealing temperatures. In C-V measurement, the inversion capacitance decreased at annealing temperature range from $500^{\circ}C$ to $700^{\circ}C$ and increased remarkably at $800^{\circ}C$. These variations may be due to the Cu diffusion through TiN into $SiO_2$ and Si.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.3
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• pp.344-349
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• 2006

The low-temperature processing is very important for fabrication of the very large scale ($60{\sim}70nm$) semiconductor devices since the submicron transistors are sensitive to the thermal budget. Hence, in this work, we propose a noble low-temperature LPCVD (Low-Pressure Chemical Vapor Deposition) process for the $SiO_2$ film and evaluate the electrical reliability of the LTO (Low-Temperature Oxide) by making the capacitors with ONO (Oxide/Nitride/Oxide) structure. The leak current of the LTO was similar to that of the high-temperature wet oxide until the electric field was lower than 5 MV/cm. However, when the electric field was higher, the LTO showed much better characteristics.