• Title/Summary/Keyword: Capacitance-voltage

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The Influence of Electrolytic Condition on Tunnel Etching and Capacitance Gain of High purity Aluminium Foil on capacitor (전해조건이 고순도 알루미늄 박 콘덴서의 터널에칭과 정전용량에 미치는 영향)

  • 이재운;이병우;김용현;이광학;김흥식
    • Journal of the Korean institute of surface engineering
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    • v.30 no.1
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    • pp.44-56
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    • 1997
  • Influence of electrochemical etching conditions on capacitance gain of aluminium electrolytic on capacitor foil has been investigated by etching cubic textured high purity aluminum foil in dilute hydrochloric acid. Uniformly distributed etch pit tunnels on aluminum surface have been obtained by pretreatment aluminium foil in 10% NaOH solution for 5 minutes followed by electrochemical etching. Electrostatic capacitance of etched aluminium foil anodized to high voltage increased with the increase of current density, total charge, temperature and concentration of electrolyte up to maximum CV-value and then deceased. Election optical observation of the etched foil revealed that the density of etch of etch pits increased with the increase of current density and concentration of electrolyte. this increase of etch pit density enlarged of the increase of capacitance. However, abnormal high current density and high electrolyte concentration induced the local dissolution of the foil surface which resulted the decrease of foil capacitance.

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An Optimized Stacked Driver for Synchronous Buck Converter

  • Lee, Dong-Keon;Lee, Sung-Chul;Jeong, Hang-Geun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.2
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    • pp.186-192
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    • 2012
  • Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

The far-end crossta1k voltage for CMOS-IC load

  • Miyao, Nobuyuki;Noguchi, Yasuaki;Matsumoto, Fujihiko
    • Proceedings of the IEEK Conference
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    • 2002.07c
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    • pp.1878-1881
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    • 2002
  • The capacitance of nonlinear component such as a CMOS inverter varies largely around the threshold voltage. We measured the far-end crosstalk of two parallel microstrip lines with the CMOS inverter load near the threshold voltage of the CMOS inverter, The negative voltage of the crosstalk agrees with that for a 4pF capacitor toad. The positive voltage of the crosstalk hardly changes of the amplitude of the input step voltage.

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Image Sticking Property in the In-Plane Switching Liquid Crystal Display by Residual DC Voltage Measurements

  • Jeon, Yong-Je;Seo, Dae-Shik;Kim, Jae-Hyung;Kim, Hyang-Yul
    • KIEE International Transactions on Electrophysics and Applications
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    • v.11C no.4
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    • pp.142-145
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    • 2001
  • The residual DC phenomena in the in-plane switching(IPS)-liquid crystal display(LCD) by the voltage-transmittance (V-T) and capacitance-voltage (C-V) hysteresis method on rubbed polyimide (PI) surfaces were studied. We found that the residual DC voltage in the IPS-LCD was decreasing with the increasing concentration of cyano LCs. The residual DC voltage of the IPS-LCD can be improved by the high polarity of cyano LCs.

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Transient Characteristics of High Voltage Flyback Transformer (고전압 플라이백 변압기의 과도특성)

  • Lim, Cheol-Woo;Park, Nam-Ju;Chung, Se-Kyo
    • Proceedings of the KIPE Conference
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    • 2000.07a
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    • pp.1-5
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    • 2000
  • This paper deals with the modeling and analysis of the high voltage flyback transformer (HVFBT) often utilized in small-sized high voltage DC power supplies. The parasitic capacitance of th HVFBT with the large turns of the secondary winding causes the undesirable parasitic resonance in the transient state which produces the high current stress and limits the switching frequency of the converter. In order to analyze this phenomenon the equivalent circuit model including the parasitic capacitance is derived and the frequency characteristics are provided. The parasitic resonance in the switching states is also investigated based on this equivalent circuit model. The derived model and analysis is finally validated through the SPICE simulation and experiments.

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A Device Parameter Extraction Method for Thin Film SOI MOSFETs (얇은 박막 SOI (Silicon-On-Insulator) MOSFET 에서의 소자 변수 추출 방법)

  • Park, Sung-Kye;Kim, Choong-Ki
    • Proceedings of the KIEE Conference
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    • 1992.07b
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    • pp.820-824
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    • 1992
  • An accurate method for extracting both Si film doping concentration and front or back silicon-to-oxide fixed charge density of fully depleted SOI devices is proposed. The method utilizes the current-to-voltage and capacitance-to-voltage characteristics of both SOI NMOSFET and PMOSFET which have the same doping concentration. The Si film doping concentration and the front or back silicon-to-oxide fixed charge density are extracted by mainpulating the respective threshold voltages of the SOI NMOSFET and PMOSFET according to the back surface condition (accumulation or inversion) and the capacitance-to-voltage characteristics of the SOI PMOSFET. Device simulations show that the proposed method has less than 10% errors for wide variations of the film doping concentration and the front or the back silicon-to-oxide fixed charge density.

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Capacitance-Voltage Characteristics of MIS Capacitors Using Polymeric Insulators

  • Park, Jae-Hoon;Choi, Jong-Sun
    • Journal of Information Display
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    • v.9 no.2
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    • pp.1-4
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    • 2008
  • In this study, we investigate the capacitance-voltage (C-V) characteristics of metal-insulator-semiconductor (MIS) capacitors consisting of pentacene, as an organic semiconductor, and polymeric insulators such as poly(4-vinylphenol) (PVP) orpolystyrene (PS) prepared by spin-coating process, to analyze the interfacial characteristics between pentacene and polymeric insulators. Compared with the device with PS, the MIS capacitor with PVP exhibited a pronounced shift in the flat-band voltage according to the bias sweep direction. This hysteric feature in the C-V characteristics is thought to be attributed to the trapped charges at the interface between pentacene and PVP owing to the hydrophilicity of PVP. From the experimental results, we can conclude that surface polarity of polymeric insulator has a critical effect on the interfacial properties, thereby affecting the bias stability of organic thin-film transistors.

Characteristics of $SnO_2$/a-Se/AI sample ($SnO_2$/a-Se/AI 소자의 특성)

  • 박계춘;정운조;유용택
    • Electrical & Electronic Materials
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    • v.7 no.1
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    • pp.7-14
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    • 1994
  • Structural and optical characteristics in $SnO_2$/a-Se/Al sample by aging variation and applying constant voltage had been investigated. a-Se was varied with monoclinic structure and its surface was greatly exchanged. Its capacitance was first decreased and then increased and its photo-current, photo-voltage and photo-capacitance were increased gradually with day and applying voltage. From the results, crystallization of a-Se and dopant trap level formation had been identified. Also, it was acknowledged $SnO_2$/a-Se/Al sample is useful in photovoltaic and solid thin film cell.

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A Circuit Design of Fingerprint Authentication Sensor (지문인식센서용 회로설계)

  • 남진문;정승민;이문기
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.4A
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    • pp.466-471
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    • 2004
  • This paper proposes an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. 1-Pixel Fingerprint sensor circuit was designed and simulated, and the layout was performed.

Fabrication of DLPC LB films with MIS structure and I-V characteristics (MIS 구조의 DLPC LB 막의 제작과 전압-전류 특성)

  • 이우선;정용호;정종상;손경춘;김상용;장의구;이경섭
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1998.06a
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    • pp.155-158
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    • 1998
  • MLS capacitor with lipid ultra thin films were deposited by Langmuir-Blodgett (LB) method on the sillicon wafer. The current versus voltage and capacitance versus voltage relationships are depend on the applied voltage, electrode area and electrode materials. LB films deposited were made of L-$\alpha$-DLPC, the 1 layer's thickness of 35$\AA$ was measured by ellipsometer. And MLS capacitor with different electrode materials, the work function of these materials was investigated to increase the leakage current. The result indicated the lower leakage current and very high saturation value of capacitance was reached within 700-800 pF when the two electrode was Ag. And $\varepsilon$$_1$, $\varepsilon$$_2$ versus photon energy showed good film formation.

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