• Journal of the Korea Society for Simulation
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• v.14 no.2
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• pp.45-55
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• 2005

There are electric double layer capacitance, polarization resistance and solution resistance in the interface between electrode and solution. Electrode process could be evaluated by the electrical impedance analysis. The necessities of the electrochemical cell analysis with high speed impedance analyzer are followings: minimization of the effects of electric stimulation on electrochemical cell and the concentration of reactive materials, and optimization of impedance signal resolution. This paper represents the design criteria for the selection and stimulation to develop fast impedance analyzer prototype for a electrochemical cell. It was suggested that the design of 470k sample/s sampling rate, 13 bit ABC resolution, and 140ms recording time is required for high speed impedance analysis system in frequency range between dc and 10kHz.

• ETRI Journal
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• v.34 no.2
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• pp.210-215
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• 2012

In this paper, a group delay time controller (GDTC) is proposed based on a reflection topology employing a parallel resonator as the reflection termination. The design equations of the proposed GDTC have been derived and validated by simulation and experimental results. The group delay time can be varied by varying the capacitance and inductance at an operating frequency. To show the validity of the proposed circuit, an experiment was performed for a wideband code division multiple access downlink band operating at 2.11 GHz to 2.17 GHz. According to the experiment, a group delay time variation of $3{\pm}0.17$ ns over bandwidth of 60 MHz with excellent flatness is obtained.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.11
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• pp.2017-2022
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• 2007

In a memory, most power is dissipated in line of high capacitance such as decoder lines, word lines, and bit * lines. The decoder size as well as the parastic capacitances of the bit-line are going to reduce, if ROM core size reduces. This paper proposes to reduce a mathod of power dissipation for reducing ROM core size. Design result of ROM used in FFT[2], proposed method lead to up to 40.6%, 42.12%, 37.82% reduction in area, power consumption and number of Tr. respectively compared with previous method.

• Proceedings of the KIEE Conference
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• 1998.07a
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• pp.67-69
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• 1998

In order to design or predict the performance of a cylindrical electrostatic motor it is necessary to analyze the torque generated by such a structure. In this paper a simple but sufficiently accurate analytical model is developed for use in design. Conformal mapping are used to model the capacitance and torque of the motor as a function of the rotor position, using a quasi-static, two-dimension approximation, the effect of an insulating dielectric layer on the stator or rotor is also evaluated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.143-151
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• 2010

In this work, we propose a single electron memory 'SEM' design which consist of two key blocs: A memory bloc, with a voltage source $V_{Mem}$, a pure capacitor connected to a tunnel junction through a metallic memory node coupled to the second bloc which is a Single Electron Transistor "SET" through a coupling capacitance. The "SET" detects the potential variation of the memory node by the injection of electrons one by one in which the drainsource current is presented during the memory charge and discharge phases. We verify the design of the SET/SEM cell by the SIMON tool. Finally, we have developed a MAPLE code to predict the retention time and nonvolatility of various SEM structures with a wide operating temperature range.

• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.228-230
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• 2009

Nowadays, the LCL-filter type becomes an attractive grid interfacing for grid-connected Voltage Source Inverter (VSI). LCL-filter can render the current harmonics attenuation around the switching frequency by using smaller inductance than L-filter. This paper presents a study about the LCL-filter design for single-phase grid-connected inverter in Photovoltaic (PV) system. According to the expected current ripple, the inductances of the filter can be determined. Based on the absorbed reactive power on capacitor, the capacitance can be calculated. Due to the theoretical analysis, a LCL-filter based single phase grid connected inverter control system are simulated. The studied simulation results are given to validate the theoretical analysis.

• Journal of Power Electronics
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• v.10 no.4
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• pp.444-449
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• 2010

The generation of electric power using self excited induction generation (SEIG) is a viable option in remote and rural areas where grid electricity is not available. The generated voltage and frequency of these machines, however, varies with varying loads. This characteristic can be resolved either by adjusting the values of the excitation capacitance or by controlling the prime mover speed. Further, in a single-point constant power application, where the machines deliver a fixed amount of power, the electronic load controller (ELC) can be used to switch-in or switch-out a dump load whenever the consumer load decreases or increases respectively. This paper presents a detailed analysis and the design of a microcontroller based SEIG -ELC system intended for stand-alone pico hydro power generation. The simulated performance of the controller is supplemented by experimental results.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.486-487
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• 2012

In this paper, novel three-port active power decoupling (APD) method for applying 250[W] micro-inverter. This type using third port for active power decoupling stores the surplus energy and supplies sufficient energy to grid. Conventional decoupling circuit is applied in single phase grid connected micro-inverter especially single-stage configuration like flyback-type DC-AC inverter. In this passive power decoupling method, electrolytic capacitor with large capacitance is needed for decoupling from constant DC power and instantaneous AC power. However the decoupling capacitor is replaced with film capacitor by using APD, thus the overall system can achieve smaller size and long lifespan. Proposed three-port flyback inverter is verified by design and simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.5
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• pp.347-352
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• 1998

In this paper, the extraction and optimization of SPICE parameters on SONOSFET for NVSM circuit design were discussed. SONOSFET devices with different channel widths and lengths were fabricated using conventional 1.2 um n-well CMOS process. And, electric properties for dc parameters and capacitance parameters were measured on wafer. SPICE parameters for the SONOSFET were extracted from the UC Berkeley level 3 model for the MOSFET. And, local optimization of Ids-Vgs curves has carried out in the bias region of subthreshold, linear, saturation respectively. Finally, the extracted SPICE parameters were optimized globally by comparing drain current (Ids), output conductance(gds), transconductance(gm) curves with theoretical curves in whole region of bias conditions. It is shown that the conventional model for the MOSFET can be applied to the SONOSFET modeling except sidewalk effect.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.139-141
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• 2019

Capacitive power transfer has an advantage in the simplicity of the energy link structure. So, the conventional phase -shift full bridge sometime is not always the best choice because of its complexity and high cost. On the other hand, the link capacitance is usually very low and requires high-frequency operation, but, the series resonant converter loses zero-voltage switching feature in the light load condition, which makes the switching loss high especially in CPT system. The paper proposes a new low-cost topology based on asymmetric half-bridge to achieve simplicity as well as wide zero voltage switching range. The design procedure is presented, and circuit operations are analyzed and verified by simulation.