• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1502-1503
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• 2007

In this paper, inductive coupled LC balun has been desi gned and simulated for embedding into an organic packaging substrate. Inductive coupling method was applied to obtain wide band characteristics, and high dielectric film was utilized to reduce a size of the balun. The proposed balun has a novel scheme which consists of three embedded LC resonators with inductive coupling. This proposed balun has relatively small inductance and capacitance values which can be easily embedded into the organic packaging substrate. Furthermore, it has a good phase imbalance characteristic. The simulated results of proposed balun are an insertion loss of 1.2 dB, a return loss of 10 dB, a phase imbalance of 1 degree at frequency bandwidth of 750 MHz ranged from 1.8 GHz to 2.55 GHz, respectively. This balun has an area of $2mm{\tims}3.5mm{\times}0.66mm$ (height).

• Journal of Power Electronics
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• 제19권1호
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• pp.296-306
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• 2019

The flyback topology is being widely used in power adapters. The coupling capacitance between primary and secondary windings of a flyback transformer is the main path for common-mode (CM) noise conduction. A Y-cap is usually used to effectively suppress EMI noise. However, this results in problems in space, cost, and the danger of safety leakage current. In this paper, the CM noise behaviors due to the electric field coupling of the transformer windings in a flyback adapter with synchronous rectification are analyzed. Then a scheme with balance winding is proposed to reduce the CM noise with a transformer winding design that eliminates the Y-cap. The planar transformer has advantages in terms of its low profile, good heat dissipation and good stray parameter consistency. Based on the proposed scheme, with the help of a full-wave simulation tool, the key parameter influences of the transformer PCB winding design on CM noise are further analyzed. Finally, a PCB transformer for an 18W adapter is designed and tested to verify the effectiveness of the balance winding scheme.

• 전자공학회논문지A
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• 제28A권5호
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• pp.355-360
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• 1991

A transmission-line discontinuities are analyzed by Finite Element Method. We use quasi-static approxmation to determine the circuit parameters of discontinuities. Delta formulation is introduced so that the cancellation error of potential calculation is reduced. To verify this method, capacitance of coaxial cable with discontinuous and coupling capacitances are calculated by modal expansion. This approach can be used for arbitrary discontinuous conducting patterns of microwave devices.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.841-844
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• 2007

In this paper, a vertical block mura, which massively occurred in the LCD products, was investigated extensively by various methods, source drain (SD) line shift is found out to be one of the key reasons. This work to some extent, establishes theoretic hypothesis for further research and solutions similar issues.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.63-64
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• 2006

In this paper, multilayer piezoelectric actuator was fabricated in order to develop ultrasonic linear motor. Multilayer actuator showed a high density of 7.78[$g/cm^3$], a large effective electromechanical coupling factor($K_{eff}$) of 0.259, a high mechanical quality factor( Qm ') of 1301, and high capacitance(c) of 19.32[nF]. Curie temperature was $343[^{\circ}C]$.

• 한국정보기술학회 영문논문지
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• 제10권1호
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• pp.37-43
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• 2020

This paper presents analysis of passive metal interconnection of the LNA block in CMOS integrated circuit. The performance of circuit is affected by the geometry of RF signal path. To investigate the effect of interconnection lines, a cascode LNA is designed, and circuit simulations with full-wave electromagnetic (EM) simulations are executed for different positions of a component. As the results, the position of an external capacitor (C_ex) changes the parasitic capacitance of electric coupling; the placement of component affects the circuit performance. This analysis of interconnection line is helpful to analyze the amount of electromagnetic coupling between the lines, and useful to choose the signal path in the layout design. The target of this work is the RF LNA enabling the seamless connection of wireless data network and the following standards have to be supported in multi-band (WCDMA: 2.11~ 2.17 GHz, CDMA200 1x : 1.84~1.87 GHz, WiBro : 2.3~2.4GHz) mobile application. This work has been simulated and verified by Cadence spectre RF tool and Ansoft HFSS. And also, this work has been implemented in a 0.13um RF CMOS technology process.

• 한국음향학회지
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• 제37권1호
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• pp.46-52
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• 2018

압전변압기에 사용되는 압전 단결정은 높은 입력 임피던스로 인하여 파워전송용량이 높지 않다는 문제점이 있다. 따라서 본 연구에서는 연산증폭기를 사용한 범용 임피던스 변환(General Impedance Convert, GIC) 회로로 구현된 정전용량 증가회로를 압전 단결정 진동자의 전기단자에 연결함으로써 입력임피던스를 저하시켜 파워전송용량을 향상시킬 수 있는 방법을 제안하였다. $128^{\circ}$회전 Y판 $LiNbO_3$ 단결정 진동자에 설계 제작된 정전용량 증가회로를 적용하여 구동 특성을 측정한 결과, 입력임피턴스는 25 % 감소, 전기-기계결합계수는 30 % 증가, 전압변환 특성에 있어서는 약 17~30배의 출력파워용량이 증가됨을 확인하였다.

• 대한전자공학회논문지SD
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• 제39권9호
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• pp.28-36
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• 2002

VLSI 영역에서 전송선에 발생하는 상호교차 커패시턴스(cross-coupling capacitance)가 중요한 이슈가 됨에 따라 이로 인한 고장을 검출하는 몇 가지 ATPG 알고리즘이 제안되었다. 대부분 단일한 능동선로만을 대상으로 연구가 진행되었으며, 테스트 생성 효율에 비해 많은 시간비용을 감수해야 하는 결과를 내 놓을 수 밖에 없었다. 이에 대한 대안으로 본 논문에서는 다중 선로를 대상으로 하는 잡음 모델에 관해 연구하였다. 본 논문은 다수의 전송선에 영향을 받는 crosstalk 모델을 제시하고 이 모델에 따라 crosstalk 잡음 고장 검출을 목적으로 하는 ATPG 알고리즘을 제안한다. 이 논문에서는 crosstalk에 의한 잡음 고장을 정적 해저드로 조건을 설정하고, 각 게이트에 따라 이 조건을 만족하는 진리표를 만들 것이다. 그 후 PODEM에 기반한 ATPG 알고리즘을 구현한 후 그 결과를 보인다.

• ETRI Journal
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• 제26권6호
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• pp.583-588
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• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• 한국전자파학회논문지
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• 제18권7호
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• pp.748-756
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• 2007

SIR(Stepped Impedance Resonator) 공진기로 구성된 대역 여파기는 특히 높은 주파수에서 fringing capacitance와 step 임피던스 불연속 영향으로 설계와 다른 왜곡된 주파수 응답을 가진다. 본 논문은 EM(Electromagnetic) 시뮬레이션을 통해 fringing capacitance와 step 임피던스 불연속 영향을 보상하는 절차를 보였다. 이 방법은 여파기에서 개별 공진기의 결합 전송선 및 결합 전송선을 연결하는 전송 선로를 체계적으로 조정하는 절차이며, 각 공진기 조정 후 제 결합하면 더 이상의 추가 조정을 요구하지 않는다. 또한, 본 방법의 타당성을 보이기 위하여 설계된 5단 SIR 여파기를 제작하여 EM 시뮬레이션 결과와 비교함으로써 방법의 타당성을 보였다.