• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.2
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• pp.177-186
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• 2012

In this paper, we propose a design method that the crosstalk of probe connector pins satisfy the limitation of -30 dB. The parameters(inductance and capacitance) were extracted in the grid-structured probe connector pin system, and it is shown that the new parameters are easily calculated with increasing ground pin numbers using the previously calculated parameters. In addition, the crosstalk reduction algorithm by employing more grounds around the signal pin has been suggested, and it is confirmed that the suggested method is quite effective especially for the reduction of inductive couplings. Finally, we suggested the correlation between the pitch and the length of the pins to satisfy the crosstalk limitation of -30 dB with the given number of ground pins, which will be quite useful when design a probe connector pin system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.10
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• pp.1036-1043
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• 2003

In this paper, novel lumped equivalent circuits for a conventional parallel directional coupler are proposed. This novel equivalent circuits only have self inductance and self capacitance, so we can design exact lumped equivalent circuit. The equivalent circuit and design formula for the presented lumped element coupler is derived based on the even- and odd-mode properties of a parallel-coupled line. By using the derived design formula, we have designed the 3 dB and 10 dB lumped element directional couplers at the center frequency of 100 MHz and 2 GHz, respectively a chip type directional coupler has been designed with multilayer configurations by employing commercial EM simulator. Designed chip-type directional couplers have a 3 dB-coupling value at the center frequency of 2 GHz and fabricated lumped directional coupler on fr4 organic substrate has a 3 dB, 10 dB-coupling values at the center frequency of 100 MHz. Excellent agreements between simulation results and measurement results on the designed directional couplers show the validity of this paper. Furthermore, in order to adapt to multi-layer process such as Low Temperature Cofired Ceramic (LTCC), chip-type lumped element couplers have been designed by using this method.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.130-137
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• 2013

This paper presents analog front-end(AFE) circuits for bio-potential measurement. The proposed AFE is composed of IA(instrument amplifier), BPF(band-pass filter), VGA(variable gain amplifier) and SAR(successive approximation register) type ADC. The low gm(LGM) circuits with current division technique and Miller capacitance with high gain amplifier enable IA to implement on-chip AC-coupling without external passive components. Spilt capacitor array with capacitor division technique and asynchronous control make the 12-b ADC with low power consumption and small die area. The total current consumption of proposed AFE is 6.3uA at 1.8V.

• Journal of IKEEE
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• v.21 no.3
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• pp.248-251
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• 2017

In this paper, The proposed board is developed by EMI compliant Dash Camera with $360^{\circ}$ omni angle. The proposed board is designed by designing DM and CM input noise reduction circuit and applying active EMI filter coupling circuit. The DM and CM input noise reduction circuit design uses a differential op amp circuit to obtain the DM noise coupled to the input signal via the parasitic capacitance(CP). In order to simplify the circuit by applying the active EMI filter coupling circuit, a noise separator is installed to compensate the noise of the EMI source to compensate the CM and DM active filter simultaneously. In order to evaluate the performance of the board for the proposed EMI response, an authorized accreditation body has confirmed that the electromagnetic certification standard for each frequency band is satisfied.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.9
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• pp.535-540
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• 2017

The changes in the electrical characteristics of CMOS ICs due to coupling with a narrow-band electromagnetic wave were analyzed in this study. A magnetron (3 kW, 2.45 GHz) was used as the narrow-band electromagnetic source. The DUT was a CMOS logic IC and the gate output was in the ON state. The malfunction of the ICs was confirmed by monitoring the variation of the gate output voltage. It was observed that malfunction (self-reset) and destruction of the ICs occurred as the electric field increased. To confirm the variation of electrical characteristics of the ICs due to the narrow-band electromagnetic wave, the pin-to-pin resistances (Vcc-GND, Vcc-Input1, Input1-GND) and input capacitance of the ICs were measured. The pin-to-pin resistances and input capacitance of the ICs before exposure to the narrow-band electromagnetic waves were $8.57M{\Omega}$ (Vcc-GND), $14.14M{\Omega}$ (Vcc-Input1), $18.24M{\Omega}$ (Input1-GND), and 5 pF (input capacitance). The ICs exposed to narrow-band electromagnetic waves showed mostly similar values, but some error values were observed, such as $2.5{\Omega}$, $50M{\Omega}$, or 71 pF. This is attributed to the breakdown of the pn junction when latch-up in CMOS occurred. In order to confirm surface damage of the ICs, the epoxy molding compound was removed and then studied with an optical microscope. In general, there was severe deterioration in the PCB trace. It is considered that the current density of the trace increased due to the electromagnetic wave, resulting in the deterioration of the trace. The results of this study can be applied as basic data for the analysis of the effect of narrow-band high-power electromagnetic waves on ICs.

• Journal of Electrical Engineering and Technology
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• v.7 no.4
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• pp.582-588
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• 2012

In this paper, a highly miniaturized and performed UWB bandpass filter has been newly designed and implemented by embedding all the passive elements into a multi-layered PCB substrate with high dielectric $SrTiO_3$ composite film for 3.1 - 4.75 GHz compact UWB system applications. The high dielectric composite film was utilized to increase the capacitance densities and quality factors of capacitors embedded into the PCB. In order to reduce the size of the filter and avoid parasitic EM coupling between the embedded filter circuit elements, it was designed by using a $3^{rd}$ order Chebyshev circuit topology and a capacitive coupled transformation technology. Independent transmission zeros were also applied for improving the attenuation of the filter at the desired stopbands. The measured insertion and return losses in the passband were better than 1.68 and 12 dB, with a minimum value of 0.78 dB. The transmission zeros of the measured response were occurred at 2.2 and 5.15 GHz resulting in excellent suppressions of 31 and 20 dB at WLAN bands of 2.4 and 5.15 GHz, respectively. The size of the fabricated bandpass filter was $2.9{\times}2.8{\times}0.55(H)mm^3$.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.12
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• pp.1458-1467
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• 1999

VLSI 공정 기술이 발달하면서 이웃한 전선 간의 간격이 점점 더 가까워 지고 있으며, 그에 따라 인접 전선 간의 혼신 문제가 심각해지고 있다. 본 논문에서는 3층 그리드 채널 배선에 적용 가능한 혼신을 최소화시키는 배선층 할당 방법을 제안한다. 이 방법은 선형 의사 불린 최적화 기법에 맞도록 고안되었으며, 적절한 변수 선택 휴리스틱과 상한값 추정 방법을 통하여 최적의 결과를 짧은 시간 안에 찾아낸다. 실험 결과를 통하여, 일반적인 0/1 정수 선형 프로그래밍 기법과 비교하여 성능과 수행시간 면에서 우수함을 보인다. Abstract Current deep-submicron VLSI technology appears to cause crosstalk problem severe since it requires adjacent wires to be placed closer and closer. In this paper, we deal with a horizontal layer assignment problem for three layer HVH channel routing to minimize coupling capacitance, a main source of crosstalk. It is formulated in a 0/1 integer linear programming problem which is then solved by a linear pseudo boolean optimization technique. Experiments show that accurate upper bound estimation technique effectively reduces crosstalk in a reasonable amount of running times.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.6
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• pp.1095-1102
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• 2010

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. High growth of the flash memory market has been driven by two combined technological efforts that are an aggressive scaling technique which doubles the memory density every year and the introduction of MLC(multi level cell) technology. Therefore, the CCI is a critical factor which affects occurring data errors in cells. We introduced an equation of CCI model and designed an equalizer reducing CCI based on the proposed equation. In the model, we have been considered the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. Also we design and verify the proposed equalizer using Matlab. As the simulation result, the error correction ratio of the equalizer shows about 20% under 20nm NAND process where the memory channel model has serious CCI.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1565_1566
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• 2009

This paper presents the design and analysis of RF Front End for Wireless Heartbeat measurement System. In this work LNA, an inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically combined to reduce the noise and the nonlinearity influences of the cascode transistors in a differential LNA. The Mixer is implemented by using the Gilbert-type configuration, cross pmos injection technique and the resonating technique for the tail capacitance. The resulting LNA achieves 1.26dB NF, better than 1.88dB NF Typical. Also Mixer resulting achieves 9.8dB at 100KHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.9
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• pp.931-935
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• 2003

A multilayer two-stage LC bandpass filter using low-temperature cofired-ceramic(LTCC) is proposed in this paper. The proposed bandpass filter is composed of two ceramic substrates with different dielectric constant instead of single ceramic material from top to bottom layer. Inductive elements are designed in a low permitivity ceramic layer to reduce parasitic effects and loss, while capacitive elements are designed in a high permitivity ceramic layer for size reduction. The proposed filter has 950 MHz center &equency, 118 MHz tractional bandwidth, and 3.5 dB insertion loss. And, the total size of this filter is 2.5${\times}$2.5${\times}$l.4mm$^3$. The performance of filter is analyzed by changing coupling capacitance between each resonator.