• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.452-455
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• 2003

[ $ZrO_2$ ] dielectric layers were grown on the p-type Si (100) substrate by metalorganic molecular beam epitaxy(MOMBE). Zrconium t-butoxide, $Zr(O{\cdot}t-C_4H_9)_4$ was used as a Zr precursor and Argon gas was used as a carrier gas. The thickness of the layers was measured by scanning electron microscopy (SEM) and the properties of the $ZrO_2$ layers were evaluated by X-ray diffraction, high frequency capacitance-voltage measurement. and HF C-V measurements have shown that $ZrO_2$ layer grown by MOMBE has a high dielectric constant (k=18-19). The growth rate is affected by various process variables such as substrate temperature, bubbler temperature, Ar, and $O_2$ gas flows.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.3
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• pp.144-148
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• 2001

For the purpose of developing capacitive humidity sensor having interdigit electrodes, interdigit electrode was modeled and simulated to obtain capacitance and sensitivity as a function of geometric parameters like the structural gap and thichness. For the development of ASIC, switched capacitor signal conditioning circuits for capacitive humidity sensor were designed and simulated by cadence using 0.25um CMOS process parameters. The signal conditioning circuits are composed of amplifier for voltage gain control, and clock generator for sensor driving and switch control The characteristics of the fabricated sensors are; 1) sensitivity is 9fF/%R.H., 2) temperature coefficient of offset(TCO) is 0.4%R.H./$^{\circ}C$, 3) nonlinearity is 1.2%FS, 4) hysteresis is 1.5%FS in humidity range of 3%R.H. ${\sim}$ 98%R.H.. The response time is 50 seconds in adsorption and 70 seconds in desorption. Fabricated process used in this capacitive humidity sensor having interdigit electrode are just as similar as conventional IC process technology. Therefore this can be easily mass produced with low cost, simple circuit and utilized in many applications for both industrial and environmental measurement and control system, such as monitoring system of environment, automobile, displayer, IC process room, and laboratory etc..

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1417-1419
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• 1997

In this paper, the dielectric properties is made researches by the dose of electron beam in order to investigate the electrical properties for transformer oils due to electron beam irradiation. To measure the dielectric loss of irradiated specimen, the liquid electrode of coaxial cylindrical shape is used, and its geometric capacitance is 16 [pF]. And the dielectric dissipation factor, $tan{\delta}$, is measured by using the Video Bridge 2150. The thermal static oven with an automatic temperature controller is used so as to apply specific temperature to specimen. This experiments for measuring the dielectric loss is performed at $20{\sim}120[^{\circ}C]$ in temperature range, $30{\sim}1.5{\times}10^5[Hz]$ in frequency and $300{\sim}500[mV]$ in voltage.

• Journal of Magnetics
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• v.19 no.2
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• pp.121-125
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• 2014

$CoFe_2O_4(CFO)/BaTiO_3(BTO)/CoFe_2O_4(CFO)$ multilayered thin films were deposited on $Pt/TiO_2/SiO_2/Si$ substrates by the pulsed laser deposition (PLD) system with KrF excimer laser (${\lambda}=248nm$). BTO, CFO, BTO/CFO and CFO/BTO/CFO structured thin films were prepared and their crystal structures and microstructures, as well as their magnetic and magneto-electrical properties, were studied. The C-V characteristics of these multilayered thin films with different capacitor structures were obtained to confirm the change in their capacitances under a magnetic field. Finally, the capacitance of the CFO/BTO/CFO thin film as a function of bias voltage under an in-plane magnetic field of 1,000 Oe increased to 951.04 pF at 1 MHz, from 831.90 pF measured under no magnetic field, indicating 14.3% increase in magnetocapacitance.

• ETRI Journal
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• v.19 no.4
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• pp.402-413
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• 1997

A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.

• Industry Promotion Research
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• v.3 no.1
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• pp.1-5
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• 2018

$SnO_2$ films were annealed in a vaccum atmosphere conditions to research the temperature dependency of current-voltage characteristics in according to the bonding structures. The $SnO_2$ film annealed in a vacuum became an amorphous structure but films annealed in an atmosphere condition had a crystal structure. The defects or depletion layer were formed by the electron-hole combination after annealing processes, and the electrical properties were changed depending on the crystal structure, binding energy and the variation of carriers. $SnO_2$ became more crystal-structural with increasing the annealing temperature, and the current increased at $SnO_2$ film annealed at $150^{\circ}C$ with Schottky current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.9
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• pp.783-789
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• 2003

The winding problems of traction motor are the major determinant of motor's life. The root cause of winding failure is gradual deterioration of the insulation due to thermal, electrical, mechanical and environmental stresses. The aging of the insulation reduces the electrical and mechanical strength of the insulation. At same point, a voltage surge or mechanical shock from a traction motor start will fracture or break down the insulation. To achieve the expected life usually requires extensive laboratory evaluation of the insulation systems and the use of accelerated aging tests. There are several nondestructive test available for checking, the condition of motor insulation, the probable extent of aging, and the rate of which aging is taking place. So the insulation characteristics of stator coil were each analyzed by measurement of dielectric loss(tan$\sigma$), capacitance and partial discharge. The method of diagnosis is able to analyze the insulation condition and evaluate the life of the traction motor.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2005.05a
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• pp.81-86
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• 2005

As the optical communication is introduced to the backbone network at first and becomes a general communication method of network, the demand of kernel parts of optical communication such as PLC(Planar Light Circuit), Coupler, and WDM(Wavelength Division Multiplexing) element increases. The alignment and the attachment technology are very important in the fabrication of optical elements. In this paper, the driving mechanism of ultra precision stage is studied with the aim of optimal design of stage. The travel and the resolution of stage are investigated. The hysteresis of the stage is generated because of PZT actuator. The hysteresis and the inverse hysteresis are modeled in X, Y, and Z-axis motion. The input data of desired displacement to the stage according to input voltage is obtained from the inverse hysteresis equation. In the result of experiments with the input data, the errors due to hysteresis are well compensated.

• Journal of Power Electronics
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• v.14 no.3
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• pp.413-420
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• 2014

The conventional Phase-Shift Full-Bridge (PSFB) converter has a serious voltage spike because of the ringing between the leakage inductance of the transformer and the parasitic output capacitance of the secondary side rectifier switches. To overcome this problem, an asynchronous active clamp technique employing an auxiliary DC/DC converter has been proposed. However, an exact analyses for designing the auxiliary DC/DC converter has not been presented. Therefore, the amount of power that is supposed to be handled in the auxiliary DC/DC converter is calculated through a precise mode analyses in this paper. In addition, this paper proposes a lossy snubber circuit with hysteresis characteristics to reduce the burden that the auxiliary DC/DC converter should take during the starting interval. This technique results in optimizing the size of the magnetic component of the auxiliary DC/DC converter. The operational principles and the theoretical analyses are validated through experiments with a 48V-to-30V/15A prototype.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.12
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• pp.1730-1736
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• 2015

This paper presents a 16-channel transimpedance amplifier (TIA) array implemented in a standard $0.18-{\mu}m$ CMOS technology for the applications of panoramic scan LADAR (PSL) systems. Since this array is the front-end circuits of the PSL systems to recover three dimensional image for unmanned vehicles, low-noise and high-gain characteristics are necessary. Thus, we propose a voltage-mode inverter TIA (I-TIA) array in this paper, of which measured results demonstrate that each channel of the array achieves $82-dB{\Omega}$ transimpedance gain, 565-MHz bandwidth for 0.5-pF photodiode capacitance, 6.7-pA/sqrt(Hz) noise current spectral density, and 33.8-mW power dissipation from a single 1.8-V supply. The measured eye-diagrams of the array confirm wide and clear eye-openings up to 1.3-Gb/s operations. Also, the optical pulse measurements estimate that the proposed 16-channel TIA array chip can detect signals within 20 meters away from the laser source. The whole chip occupies the area of $5.0{\times}1.1mm^2$ including I/O pads. For comparison, a current-mode 16-channel TIA array is also realized in the same $0.18-{\mu}m$ CMOS technology, which exploits regulated-cascode (RGC) input configuration. Measurements reveal that the I-TIA array achieves superior performance in optical pulse measurements.