• Journal of electromagnetic engineering and science
• /
• 제1권1호
• /
• pp.78-82
• /
• 2001

For fast capacitance computation, a simple mesh refinement technique on MLFMA(Multi-Level Fast Multipole Algorithm) is proposed The triangular meshes are refined mainly in the area which has heavy charge density. The technique is applied to the capacitance extraction of three dimensional conductors. The results show good convergence with comparable accuracy. An adaptive technique concerned with MLFMA is useful to reduce computation time and the number of elements without additional computational efforts in large three dimensional problems.

• Bulletin of the Korean Chemical Society
• /
• 제17권4호
• /
• pp.349-352
• /
• 1996

Electrical capacitance at the interface between electrolyte solution and conducting polypyrrole film electrode was measured by a simple electrochemical method. The polymer films were electropolymerized in the presence of perchlorate (PPy-ClO4) or Nafion (PPy-Nafion) anions as the dopant ions. Both polymers exhibited large double layer capacitances which were slightly potential dependent within the potential range where the polymers are conductive. The capacitance increased in proportion to the polymer thickness. The specific capacitance were about 10 Fg-1and 44 F g-1 for PPy-Nafion and PPy-ClO4, respectively.

• 대한전자공학회논문지SD
• /
• 제43권10호
• /
• pp.90-96
• /
• 2006

본 논문에서는 capacitance scaling 구조를 이용하여 짧은 locking 시간과 작은 fractional spur를 가지는 ${\Sigma}{\Delta}$ fractional-N PLL을 설계하였다. 루프필터의 실효 커패시턴스를 변화시키기 위하여 여러 개의 전하펌프를 이용해 서로 다른 경로로 커패시터에 전류를 공급하였다. 필터의 실효 커패시턴스는 동작상태에 따라 크기가 변하며 커패시터들은 하나의 PLL 칩에 집적화 할 수 있을 정도로 작은 크기를 가진다. 또한 PLL이 lock 되면 전하펌프 전류의 크기도 작아져 fractional spur의 크기도 작아진다. 제안된 구조는 HSPICE CMOS $0.35{\mu}m$ 공정으로 시뮬레이션 하였으며 $8{\mu}s$ 이하의 locking 시간을 가진다. PLL의 루프필터는 200pF, 17pF의 작은 커패시터와 $2.8k{\Omega}$의 저항으로 설계되었다.

• Composites Research
• /
• 제26권6호
• /
• pp.337-342
• /
• 2013

나노입자를 이용하여 강화 효과를 높이기 위해서는 고분자 기지 내부의 균일한 분산 상태를 확보하여야 한다. 또한 균일분산 조건 확보 후 균일 분산상태를 증명할 평가자료가 필요하다. 본 연구는 에폭시 수지와 SiC 나노입자를 혼합한 SiC/에폭시 복합 수지를 제조할 경우 커패시턴스 측정법을 이용한 강화재 분산도 예측 연구를 진행하였다. 커패시턴스는 전기용량을 의미하며 측정 재료의 내부 전하량과 비례한다. 기존 에폭시 수지에 비해 나노 SiC 입자를 함유할 경우 전하량이 증가되는 이론을 바탕으로 구간별 커패시턴스 측정에 따른 분산도 평가를 진행하고, 커패시턴스 분산도 예측방법에 대한 타당성을 FE-SEM과 물리적 강도 증가 방법으로 평가하였다. 소니케이션 분산 방법과 교반기 분산 방법을 이용하여 분산 방법에 따른 SiC 나노입자 분산도 상태를 비교하였다. 인장강도와 커패시턴스 간의 상관관계가 있었으며, 파단면에 대한 비교를 할 때 분산성 향상에 대한 차이를 확인할 수 있었다.

• 전력전자학회논문지
• /
• 제21권6호
• /
• pp.514-524
• /
• 2016

This work suggests a study on 5 kW plasma power supply design and reactor capacitance estimation algorithm for a wide range of linear output control to operate a plasma reactor. The suggested study is designed to use a two-stage circuit and control the full-bridge circuit of the two-stage circuit using the buck converter output voltage of the single-stage circuit. The switching frequency of the full-bridge circuit is designed to operate through high-frequency switching and obtain maximum output using LC parallel resonance. Soft switching technique(ZVS) is used to reduce the loss caused by high-frequency switching, and duty control of the buck converter is applied to control a wide range of linear output. The internal capacitance of the reactor cannot easily be extracted, and thus, the reactor cannot be operated in an optimized resonant state. To address this issue, this work designs the internal capacitance of the reactor such that estimations can be performed with the developed reactor capacitance estimation algorithm applied to the internal capacitance of the reactor. A 5 kW plasma power supply is designed for a wide range of linear output control, and the validity of the study on the reactor capacitance estimation algorithm is verified.

• Transactions on Electrical and Electronic Materials
• /
• 제17권5호
• /
• pp.293-296
• /
• 2016

Using capacitance-voltage (C-V) and conductance-voltage (G/ω-V) measurements, the electrical properties of Cu/n-InP Schottky diodes were investigated. The values of C and G/ω were found to decrease with increasing frequency. The presence of interface states might cause excess capacitance, leading to frequency dispersion. The negative capacitance was observed under a forward bias voltage, which may be due to contact injection, interface states or minority-carrier injection. The barrier heights from C-V measurements were found to depend on the frequency. In particular, the barrier height at 200 kHz was found to be 0.65 eV, which was similar to the flat band barrier height of 0.66 eV.

• 전기학회논문지
• /
• 제56권1호
• /
• pp.81-87
• /
• 2007

This paper proposes a new capacitance estimation scheme for a DC-link capacitor in a three-phase AC/DC/AC PWM converter. A controlled AC voltage with a lower frequency than the line frequency is injected into the DC-link voltage, which then causes AC power ripples at the DC side. By extracting the AC voltage and power components on the DC output side using digital filters, the capacitance can then be calculated using the Support Vector Regression (SVR). By training of SVR, a function which relates a given input (capacitor's power) and its corresponding output (capacitance value) can be derived. This function is used to predict outputs for given inputs that are not included in the training set. The proposed method does not require the information of DC-link current and can be simply implemented with only software and no additional hardware. Experimental results confirm that the estimation error is less than 0.16%.

• 전자공학회논문지
• /
• 제53권4호
• /
• pp.136-141
• /
• 2016

본 논문에서는 Current Modulator를 이용하여 루프 필터 커패시턴스 유효 용량을 배가 시켜 칩 크기를 줄일 수 있는 위상 고정루프를 제안하였다. 제안된 위상고정루프에서는 Current Modulator로 루프 필터의 커패시턴스 유효 용량을 배가 시켜 루프 필터 커패시터 크기를 1/10로 줄였다. 제안된 위상고정루프는 1.8V $0.18{\mu}m$ CMOS 공정을 이용하여 설계되었다. 시뮬레이션 결과는 기존 구조와 같은 잡음 특성과 위상고정 시간을 보여주었다.

• 한국전자파학회:학술대회논문집
• /
• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
• /
• pp.638-648
• /
• 2003

An active capacitance circuit is analyzed in depth and its application to active RF BPF with low noise figure is discussed. The characteristics of the active capacitance circuit made of FET[1] exhibits negative resistance and conventional capacitance, which is easily controlled. However, it is difficult to make the negative resistance adequate in the designated frequency range due to the lack of detailed analysis, which could make an active circuit unstable as the frequency is going higher or lower. In this paper, we analyzed the negative resistance characteristics of active capacitance circuits and also presented the method that the flatness of passband can be controlled. Finally we have designed a 4-stage active BPE, which results in bandwidth of 100 MHz, 0,04 dB insertion loss, 0.2 dB ripple, and noise figure of 2.4 dB at 1.75 GHz band.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
• /
• pp.93-96
• /
• 2001

We have reported to make nanostructured cobalt oxide electrode that have large capacitance over than 400F/g (specific capacitance) and good cycleability. But, It had serious demerits of low voltage range under 0.5V and low power density. Therefore, we need to increase voltage range of cobalt oxide electrode. we report here on the electrochemical properties of sol-gel-derived nanoparticulate cobalt xerogel in 1M KOH solution and aqueous polymeric gel electrolyte. In solution electrolyte, cobalt oxide electrode had over than 250F/g capacitance consisted of EDLC and pseudocapacitance. In gel electrolyte, cobalt oxide electrode had around l00F/g capacitance. This capacitance was only surface EDLC. In solution electrolyte, potassium ion as working ion reacted with both of layers easily. However, In gel electrolyte, reacted with only surface-active layer. Its very hard to reach resistive layer. So, we have studied on pretreatment of electrode to contain working ions easily. We'll report more details.