• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.35-41
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• 2012

Due to the technology scaling, more transistors can be placed on a cache memories of a processor. However, processors become more vulnerable to the soft error because of the highly integrated transistors, and consequently, the reliability of the cache memory must consider seriously at the design space level. In this paper, we propose the reliability improving technique which can be achieved with low energy and low area overheads. The simulation experiments of the proposed scheme shows over 95.4% of protection rate against the soft error with only 0.26% of performance degradations. Also, It requires only 2.96% of extra energy consumption.

• The KIPS Transactions:PartC
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• v.15C no.4
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• pp.227-238
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• 2008

As the internet users rise up rapidly, DNS information forgery can cause severe socio-economic damages. However, most studies on DNS information security reached the breaking point in applying to actual circumstances because of the limit of existing DNS system version, the increasement of management burden and etc. The paper proposes the real-time method for detecting cache poisoning of DNS system independent of analysing the DNS forgery types in the current DNS service environment. It also proposes the method of enhancing the reliability for the cache information of Recursive DNS system by post-verifying the cache information of the DNS system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.1
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• pp.15-21
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• 2014

Due to the development of manufacturing technology scaling, more transistors can be placed on a cache memories of a processor. However, processors become more vulnerable to the soft errors because of highly integrated transistors, the reliability of cache memory must consider seriously at the design level. Various researches are proposed to overcome the vulnerability of soft error, but researches of tag bit are proposed very rarely. In this paper, we revaluate the reliability improvement technique for tag bit, and analyse the protection rate of write-back operation, which is a typical case of not satisfying temporal locality. We also propose the methodology to improve the protection rate of write-back operation. The experiments of the proposed scheme shows up to 76.8% protection rate without performance degradations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2441-2446
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• 2009

Wireless Sensor Network collects a data from the specific area and the control is composed of small sensor nodes. Like this sensors to after that is established at the beginning are operated with the battery, the operational duration until several years must be continued from several months and will be able to apply the resources which is restricted in efficiently there must be. In this paper RHC (rounting history cache) applies in Directed Diffusion which apply a data central concept a reliability and an efficiency in data transfer course set. RHC algorithms which proposes each sensor node updated RHC of oneself with periodic and because storing the optimization course the course and, every event occurrence hour they reset the energy is wasted the fact that a reliability with minimization of duplication message improved.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.1018-1021
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• 2009

Wireless Sensor Network collects a data from the specific area and the control is composed of small sensor nodes. Like this sensors to after that is established at the beginning are operated with the battery, the operational duration until several years must be continued from several months and will be able to apply the resources which is restricted in efficiently there must be. In this paper RHC (rounting history cache) applies in Directed Diffusion which apply a data central concept a reliability and an efficiency in data transfer course set. RHC algorithms which proposes each sensor node updated RHC of oneself with periodic and because storing the optimization course the course and, every event occurrence hour they reset the energy is wasted the fact that a reliability with minimization of duplication message improved.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.11
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• pp.409-418
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• 2014

The amount of data located in storage servers has dramatically increased with the growth in cloud and social networking services. Storage systems with very large capacities may suffer from poor reliability and long latency, problems which can be addressed by the use of a hybrid disk, in which mechanical and flash memory storage are combined. The Linux-based SSD(solid-state disk) uses a caching technique based on the DM-cache utility. We assess the limitations of DM-cache by evaluating its performance in diverse environments, and identify problems with the caching policy that it operates in response to various commands. This policy is effective in reducing latency when Linux is running in native mode; but when Linux is installed as a guest operating systems on a virtual machine, the overhead incurred by caching actually reduces performance.

• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.1-12
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• 2010

Recently, processor performance has been improved dramatically. Unfortunately, as the process technology scales down, energy consumption in a processor increases significantly whereas the processor performance continues to improve. Moreover, peak temperature in the processor increases dramatically due to the increased power density, resulting in serious thermal problem. For this reason, performance, energy consumption and thermal problem should be considered together when designing up-to-date processors. This paper proposes three modified filter cache schemes to alleviate the thermal problem in the filter cache, which is one of the most energy-efficient design techniques in the hierarchical memory systems : Bypass Filter Cache (BFC), Duplicated Filter Cache (DFC) and Partitioned Filter Cache (PFC). BFC scheme enables the direct access to the L1 cache when the temperature on the filter cache exceeds the threshold, leading to reduced temperature on the filter cache. DFC scheme lowers temperature on the filter cache by appending an additional filter cache to the existing filter cache. The filter cache for PFC scheme is composed of two half-size filter caches to lower the temperature on the filter cache by reducing the access frequency. According to our simulations using Wattch and Hotspot, the proposed partitioned filter cache shows the lowest peak temperature on the filter cache, leading to higher reliability in the processor.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.2
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• pp.247-251
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• 2010

Using SCM in storage systems introduce new potentials for improving I/O performance and reliability. In this paper, we study the use of SCM as a buffer cache that guarantees transactional unit writes. Our proposed method can improve storage system reliability and performance at the same time and can recover the storage system immediately upon a system crash. The Proposed method is based on the LINUX JBD(Journaling Block Device), thus reliability is equivalent to JBD. In our experiments, the file system that adopts our method shows better I/O performance even while guaranteeing high reliability and shows fast file system recovery time (about 0.2 seconds).

• The KIPS Transactions:PartA
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• v.10A no.2
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• pp.83-92
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• 2003

RAID 5 is a widely-used technique used to construct disk systems of high reliability and performance. This paper proposes APGOC (Adaptive Parity Group On Cache) organization on cache to solve "small write" problem of RAID 5 especially in OLTP (On-Line Transaction Processing System) environments. In our approach, when user process makes a request for a file to kernel, the information on the read/write characteristics is added to the file data structure of the file system. With this information, data and parity cache can be managed interchangeably through parity fetching. Therefore we can enhance the cache utilization and improve the disk request response time. Our method is analyzed and evaluated with a simulation method. Comparing with previous works, we observed about 6~l3% of performance enhancement.hancement.

• Journal of Computing Science and Engineering
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• v.7 no.1
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• pp.67-80
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• 2013

The worst-case execution time (WCET) of each real-time task in multicore processors with shared caches can be significantly affected by inter-thread cache interferences. The worst-case inter-thread cache interferences are dependent on how tasks are scheduled to run on different cores. Therefore, there is a circular dependence between real-time task scheduling, the worst-case inter-thread cache interferences, and WCET in multicore processors, which is not the case for single-core processors. To address this challenging problem, we present an offline real-time scheduling approach for multicore processors by considering the worst-case inter-thread interferences on shared L2 caches. Our scheduling approach uses a greedy heuristic to generate safe schedules while minimizing the worst-case inter-thread shared L2 cache interferences and WCET. The experimental results demonstrate that the proposed approach can reduce the utilization of the resulting schedule by about 12% on average compared to the cyclic multicore scheduling approaches in our theoretical model. Our evaluation indicates that the enhanced scheduling approach is more likely to generate feasible and safe schedules with stricter timing constraints in multicore real-time systems.