• The KIPS Transactions:PartA
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• v.13A no.7 s.104
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• pp.615-622
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• 2006

Caching in a Wireless Internet Proxy Server Cluster Environment has an effect that minimizes the time on the request and response of Internet traffic and Web user As a way to increase the hit ratio of cache, we can use a hash function to make the same request URLs to be assigned to the same cache server. The disadvantage of the hashing scheme is that client requests cannot be well-distributed to all cache servers so that the performance of the whole system can depend on only a few busy servers. In this paper, we propose an improved load balancing scheme using hashing and Round Robin scheme that distributes client requests evenly to cache servers. In the existing hashing scheme, if a hashing value for a request URL is calculated, the server number is statically fixed at compile time while in the proposed scheme it is dynamically fixed at run time using round robin method. We implemented the proposed scheme in a Wireless Internet Proxy Server Cluster Environment and performed experiments using 16 PCs. Experimental results show the even distribution of client requests and the 52% to 112% performance improvement compared to the existing hashing method.

• Journal of Digital Contents Society
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• v.9 no.4
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• pp.653-659
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• 2008

With the recent explosion in using of the Internet, the problem of caching web objects has gained considerable importance. Caching on the Internet differs from traditional caching in several ways. Especially, the conventional caching algorithms are not well suited for the Internet caching. The poor performance is mainly due to its unfair treatment of small objects since all the objects are treated the same even though they differ in size. In this paper, I give an overview of caching policies designed for web objects, and provide a new algorithm of my own. I also have performed trace-driven simulations about variable-size replacement algorithms, and derived a new algorithm to improve byte hit-ratio by classifying objects based on their sizes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• The Journal of the Korea Contents Association
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• v.8 no.11
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• pp.57-64
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• 2008

The data grid computing provides geographically distributed storage resources to solve computational problems with large-scale data. Unlike cache replacement policies in virtual memory or web-caching replacement, an optimal file replacement policy for data grids is the one of the important problems by the fact that file size is very large. The traditional file replacement policies such as LRU(Least Recently Used), LCB-K(Least Cost Beneficial based on K), EBR(Economic-based cache replacement), LVCT(Least Value-based on Caching Time) have the problem that they have to predict requests or need additional resources to file replacement. To solve theses problems, this paper propose SBR-k(Sized-based replacement-k) that replaces files based on file size. The proposed policy considers file size to reduce the number of files corresponding to a requested file rather than forecasting the uncertain future for replacement. The results of the simulation show that hit ratio was similar when the cache size was small, but the proposed policy was superior to traditional policies when the cache size was large.

• Journal of Digital Convergence
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• v.11 no.11
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• pp.421-427
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• 2013

Disk Cache Manager(DCM), a functional server of microkernel based, to improve the I/O power of shared disks is designed and implemented in this work. DCM interfaces other different servers with message passing through ports by serving as a system actor the multi-thread mode on the Minix3 micro-kernel. DCM proposed in this paper uses the shared disk logically as a Seven Disk and Sodd Disk to enable parallel I/O. DCM enables the efficient placement of disk data because it raises disk cache hit-ratio by increasing the cache size when the utilization of the particular disk is high. Through experimental results, we show that DCM is quite efficient for a shared disk with higher utilization.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.4
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• pp.71-79
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• 2016

This study proposes a performance model of a shared bus multi-processor system and analyzes the effect of input/output types on system performance and overload of shared resources. This system performance model reflects the memory reference time in relation to the effect of input/output types on shared resources and the input/output processing time in relation to the input/output processor, disk buffer, and device standby places. In addition, it demonstrates the contribution of input/output types to system performance for comprehensive analysis of system performance. As the concept of workload in the probability theory and the presented model are utilized, the result of operating and analyzing the model in various conditions of processor capability, cache miss ratio, page fault ratio, disk buffer hit ratio (input/output processor and controller), memory access time, and input/output block size. A simulation is conducted to verify the analysis result.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8A
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• pp.1115-1123
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• 2000

Most of the existing web caches are used in huge organizations. But many internet users belong to small organizations such as a venture company or a PC room. Users are in general in multiple window environments, and use several programs concurrently with rapid preference change within a relatively short period of time. We develop a network-path based algorithm. It organizes a cache according to the network paths of the requested URLs and builds a network cache farm where caches are logically connected with each other and each cache has its own preference over certain network paths. The algorithm has been implemented and tested in a real site. The performance results show that the new algorithm outperforms the existing algorithms in the hit ratio and response time dramatically with low cost.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.3
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• pp.371-375
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• 2010

SSD is a storage medium based on NAND Flash memory. Because of its short latency, low power consumption, and resistance to shock, it's not only used in PC but also in server computers. Most SSDs use FTL to overcome the erase-before-overwrite characteristic of NAND flash. There are several types of FTL, but page mapped FTL shows better performance than others. But its usefulness is limited because of its large memory footprint for the mapping table. For example, 64MB memory space is required only for the mapping table for a 64GB MLC SSD. In this paper, we propose a novel caching scheme for the mapping table. By using the mapping-table-meta-data we construct a fully associative cache, and translate the address within O(1) time. The simulation results show more than 80 hit ratio with 32KB cache and 90% with 512KB cache. The overall memory footprint was only 1.9% of 64MB. The time overhead of cache miss was measured lower than 2% for most workload.

• The Journal of Society for e-Business Studies
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• v.12 no.3
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• pp.211-234
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• 2007

In e-business, XML is a major format of data and it is essential to efficiently process queries against XML data. XML query caching has received much attention for query performance improvement. In employing XML query caching, some efficient technique of cache replacement is required. The previous techniques considered as a replacement unit either the whole query result or the path in the query result. The former is simple to employ but it is not efficient whereas the latter is more efficient and yet the size difference among the potential victims is large, and thus, efficiency of caching would be limited. In this paper, we propose a new technique where the element in the query result is are placement unit to overcome the limitations of the previous techniques. The proposed technique could enhance the cache efficiency to a great extent because it would not pick a victim whose size is too large to store a new cached item, the variance in the size of victims would be small, and the unused space of the cache storage would be small. A technique of XML semantic cache replacement is presented which is based on the replacement function that takes into account cache hit ratio, last access time, fetch time, size of XML semantic region, size of element in XML semantic region, etc. We implemented a prototype XML semantic cache system that employs the proposed technique, and conducted a detailed set of experiments over a LAN environment. The experimental results showed that our proposed technique outperformed the previous ones.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.2
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• pp.288-299
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• 1993

This paper proposes the new bus protocol in the tightly coupled multiprocessor system. The bus protocol uses the pipelined data transfer and block transfer scheme to increase the bus bandwidth, The bus also has the independent transfer lines for the address and data respectively, and it can transfer the data up to maximum 264 Mbytes /sec. This paper also models the multiprocessor system where each processor boards have the private cache. Simulation evaluates the bus and system performance according to hit ratio of the reference data in cache memory, In the case of using this bus, the bus is evaluated not to be saturated when up to 10 processor boards are connected to the bus. As for up to 4 memory interleavng, the performance increases linearly.