• Journal of Mechanical Science and Technology
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• v.18 no.1
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• pp.12-19
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• 2004

Using LSM (laser scanning method) , the radius of curvature due to thermal deformation in polyimide film coated on Si substrate is measured. Since the polyimide film shows viscoelastic behavior, i.e., the modulus and deformation of the film vary with time and temperature, we estimate the relaxation modulus and the residual stresses of the polyimide film by measuring the radius of curvature and subsequently by performing viscoelastic analysis. The residual stresses relax by an amount of 10％ at 100$^{\circ}C$ and 20% at 150$^{\circ}C$ for two hours.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1337-1342
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• 2008

The whisker grows at the plating of a lead frame so that it causes the serious problem like the short. To prove this case, many people have studied the cause and influence of the tin whisker growth. This study explains the grain size affects the growth of the whisker in the lead frame. By these studies about the whisker, the whisker growth is discovered by stresses generated by the intermetallic compound and CTE mismatch in both plating and base metal. The stresses or lattice defect generated in the plating process changes grain structure of plating. Consequently, these various stresses are stabilized by forming unspecified whiskers through lots of grain boundaries. Because the grain boundary is the path of the whisker growth, the smaller grain size exists, the more whiskers grow.

• Transactions of Materials Processing
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• v.18 no.6
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• pp.482-487
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• 2009

A finite element based microstructural modeling for the size dependent strengthening of particle reinforced aluminum composites is presented. The model accounts explicitly for the enhanced strength in a discretely defined "punched zone" around the particle in an aluminum matrix composite as a result of geometrically necessary dislocations developed through a CTE mismatch. The density of geometrically necessary dislocations is calculated considering volume fraction of the particle. Results show that predicted flow stresses with different particle size are in good agreement with experiments. It is also shown that 0.2% offset yield stresses increases with smaller particles and larger volume fractions and this length-scale effect on the enhanced strength can be observed by explicitly including GND region around the particle. The strengths predicted with the inclusion of volume fraction in the density equation are slightly lower than those without.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2009.05a
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• pp.322-325
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• 2009

An enhanced continuum model for the size dependent strengthening of particle reinforced composites is presented. The model accounts explicitly for the enhanced strength in a discretely defined "punched zone" around the particle in a metal matrix composite as a result of geometrically necessary dislocations developed through a CTE mismatch. The size of the punched zone presents an intrinsic length scale, and this results in the size dependence of the overall behavior of the composite. Results show that predicted 0.2% offset yield stresses are increasing with smaller inclusions and larger volume fractions and this length-scale effect on the enhanced strength can be observed by explicitly including GND region around the particle.

• Macromolecular Research
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• v.12 no.1
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• pp.78-84
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• 2004

Advanced epoxy molding compounds (EMCs) should be considered to alleviate the thermal stress problems caused by low thermal conductivity and high elastic modulus of an EMC and by the mismatch of the coefficient of thermal expansion (CTE) between an EMC and the Si-wafer. Though A1N has some advantages, such as high thermal conductivity and mechanical strength, an A1N-filled EMC could not be applied to commercial products because of its low fluidity and high modules. To solve this problem, we used 2-$\mu\textrm{m}$ fused silica, which has low porosity and spherical shape, as a small size filler in the binary mixture of fillers. When the composition of the silica in the binary filler system reached 0.3, the fluidity of EMC was improved more than twofold and the mechanical strength was improved 1.5 times, relative to the 23-$\mu\textrm{m}$ A1N-filled EMC. In addition, the values of the elastic modules and the dielectric constant were reduced to 90％, although the thermal conductivity of EMC was reduced from 4.3 to 2.5 W/m-K, when compared with the 23-$\mu\textrm{m}$ A1N-filled EMC. Thus, the A1N/silica (7/3)-filled EMC effectively meets the requirements of an advanced electronic packaging material for commercial products, such as high thermal conductivity (more than 2 W/m-K), high fluidity, low elastic modules, low dielectric constant, and low CTE.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.2
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• pp.13-21
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• 1999

Flip chip assembly directly on organic boards offers miniaturization of package size as well as reduction in interconnection distances resulting in a high performance and cost-competitive Packaging method. This paper describes the investigation of alternative low cost flip-chip mounting processes using electroless Ni/Au bump and anisotropic conductive adhesives/films as an interconnection material on organic boards such as FR-4. As bumps for flip chip, electroless Ni/Au plating was performed and characterized in mechanical and metallurgical point of view. Effect of annealing on Ni bump characteristics informed that the formation of crystalline nickel with $Ni_3$P precipitation above $300^{\circ}C$ causes an increase of hardness and an increase of the intrinsic stress resulting in a reliability limitation. As an interconnection material, modified ACFs composed of nickel conductive fillers for electrical conductor and non-conductive inorganic fillers for modification of film properties such as coefficient of thermal expansion(CTE) and tensile strength were formulated for improved electrical and mechanical properties of ACF interconnection. The thermal fatigue life of ACA/F flip chip on organic board limited by the thermal expansion mismatch between the chip and the board could be increased by a modified ACA/F. Three ACF materials with different CTE values were prepared and bonded between Si chip and FR-4 board for the thermal strain measurement using moire interferometry. The thermal strain of ACF interconnection layer induced by temperature excursion of $80^{\circ}C$ was decreased with decreasing CTEs of ACF materials.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.1-10
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• 2022

Recently, semiconductor devices have been used in many fields owing to various applications of mobile electronics, wearable and flexible devices and substrates. During the semiconductor chip bonding process, the mismatch of coefficient of therm al expansion (CTE) between the substrate and the solder, and the excessive heat applied to the entire substrate and components affect the performance and reliability of the device. These problems can cause warpage and deterioration of long-term reliability of the electronic packages. In order to improve these issues, many studies on low-melting temperature solders, which is capable of performing a low-temperature process, have been actively conducted. Among the various low-melting temperature solders, such as Sn-Bi and Sn-In, Sn-58Bi solder is attracting attention as a promising low-temperature solder because of its advantages such as high yield strength, moderate mechanical property, and low cost. However, due to the high brittleness of Bi, improvement of the Sn-Bi solder is needed. In this review paper, recent research trends to improve the mechanical properties of Sn-Bi solder by adding trace elements or particles were introduced and compared.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.10a
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• pp.67-73
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• 2006

A system in package (SiP) generally contains a variety of systems such as analog, digital, optical and micro-electro-mechanical systems, integrated in a system-level package connected through a substrate. However, there are many electrical and mechanical reliability issues including the reliability issue for embedded structures. A mismatch of thermal coefficients of expansion among packaging materials and devices can lead to warping or delamination in the package. In this study, the effect of material properties of underfill, such as Young's modulus and CTE, are investigated through FEM simulation. Experimental investigation on the warpage of the package is also carried out to verify the simulation results. The results show that the reliability of the system in package is closely related to the material properties of underfill. The results of this study provide a good guidance for the material selection when designing the system in package.

• Transactions on Electrical and Electronic Materials
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• v.6 no.4
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• pp.135-139
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• 2005

In this paper, negative SU-8 photoresist processed at low temperature is characterized in terms of delamination. Based on a $3^3$ factorial designed experiment, 27 samples are fabricated, and the degree of delamination is measured for each. In addition, nine samples are fabricated for the purpose of verification. Employing the. neural network modeling technique, a process model is established, and response surfaces are generated to investigate degree of delamination associated with three process parameters: post exposure bake (PEB) temperature, PEB time, and exposure energy. From the response surfaces generated, two significant parameters associated with delamination are identified, and their effects on delamination are analyzed. Higher PEB temperature at a fixed PEB time results in a greater degree of delamination. In addition, a higher dose of exposure energy lowers the temperature at which the delamination begins and also results in a larger degree of delamination. These results identify acceptable ranges of the three process variables to avoid delamination of SU-8 film, which in turn might lead to potential defects in MEMS device fabrication.