• Journal of Sensor Science and Technology
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• v.12 no.1
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• pp.44-50
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• 2003

A security system consisted of an infrared sensor and PLD(Programmable Logic Device) was fabricated to prevent an intruder. The fabricated system detect the intruder using infrared sensor and has password key pad to permit someone to enter the house and office. The control circuit of the system is designed by VHDL(Very high speed integrated Hardware Description Language). The system was demonstrated in various conditions and the output signals were displayed in LCD, LED, buzzer and so on. This designed system in this paper has a advantage to supplement additional function with ease.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.1
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• pp.88-95
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• 2004

Micro stepping method is adopted in order to eliminate effectively the resonant phenomena and to increase the positional resolution. Exist micro-step method by using Sinusoidal waveform, drive circuit is complex by using micro controller and ROM, it have fault on cost Increase. This paper proposed trapezoidal current wave form for simple control circuit and micro stepping method by using a low cost controller. This paper proposed method verify by using CPLD(EPM9320RC208-15) of low cost. This paper make experiment that comparison of exist method and proposed method. This paper obstruct a escape of motor by using high speed detect.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.84-91
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• 2002

In this paper, we proposed a CLB-based CPLD technology mapping algorithm for power minimization under time constraint in combinational circuit. The main idea of our algorithm is to exploit the "cut enumeration and feasible cluster" technique to generate possible mapping solutions for the sub-circuit rooted at each node. In our technology mapping algorithm conducted a low power by calculating TD and EP of each node and decomposing them on the circuit composed of DAG. It also takes the number of input, output, and OR-term into account on condition that mapping can be done up to the base of CLB, and so it generates the feasible clusters to meet the condition of time constraint. Of the feasible clusters, we should first be mapping the one that h3s the least output for technology mapping of power minimization and choose to map the other to meet the condition of time constraint afterwards. To demonstrate the efficiency of our approach, we applied our algorithm to MCNC benchmarks and compared the results with those of the exiting algorithms. The experimental results show that our approach is shown a decrease of 46.79% compared with DDMAP and that of 24.38% for TEMPLA in the power consumption.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.8
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• pp.767-773
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• 2008

This paper presents a localization system based on the use of electric compass and tracking IR light source. Digital RGB(Red, Green, Blue)signal of digital CMOS Camera is sent to CPLD which converts the color image to binary image at 30 frames per second. CMOS camera has IR filter and UV filter in front of CMOS cell. The filters cut off above 720nm light source. Binary output data of CPLD is sent to DSP that rapidly tracks the IR light source by moving Camera tilt DC motor. At a robot toward north, electric compass signals and IR light source angles which are used for calculating the data of the location system. Because geomagnetic field is linear in local position, this location system is possible. Finally, it is shown that position error is within ${\pm}1.3cm$ in this system.

• Journal of Electrical Engineering and Technology
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• v.5 no.4
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• pp.623-630
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• 2010

This paper presents the implementation and characteristic analysis of a drive system for a three-phase permanent magnet motor with independent excitation winding that is applicable for electric bicycles. The design features improves the phase current waveform, output power, and torque by using advance angle control. This adjusts the phase angle of each phase current in relation to back EMF. In addition, a DC-side PI current control is performed through PWM generation circuit using a low-cost one-chip microcontroller and a CPLD chip, resulting in reduced system costs. Finally, the validity of this control scheme for driving electric bicycles and output/torque improvement characteristics are verified through analysis and experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.5B
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• pp.572-581
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• 2001

본 논문에서는 위성통신에서 강우감쇠에 따라 가변 부호화율을 적용시킬 수 있는 적응형 부호화 기법에 대한 연구를 하였다. 따라서, 3bit 연판정을 적용한 Viterbi 복호기를 이용하여 QPSK와 TC-8PSK 신호를 복호할 수 있는 pragmatic TCM과 LSB 부호화 알고리즘에 대해 여러 부호화율에서 성능분석을 하였다. 또한 구현을 위한 최적의 파라미터를 설정하여 부호화율 2/3를 가지는 pragmatic TCM을 VHDL 모델링 하였다. 구현결과 PLEX10KE100EQC208-1 CPLD 칩으로 구현 가능하였으며, 42.36 Mbps의 복호 속도를 가진다. 실제 ASIC 설계시 CPLD 속도보다 약 5∼6배의 고속화가 가능하므로, 200 MHz 트렌스 폰더를 갖는 Ka 대역 초고속 위성통신 시스템에서 강우 감쇠에 대처하기 위한 적응형 트렐리스 부호화방식에 적용할 수 있다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2007.04a
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• pp.275-275
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• 2007

아날로그와 디지털 신호를 혼용해서 구현할 수 있는 Cypress 의 PSoC(Programmable System-On-Chip)의 구조와 전기적, 기계적 특성을 소개하고 기존의 u-P, FPGA, CPLD 와의 차별적 특징을 살펴보고 디자인 툴을 활용한 Program방법을 예시하였다. 현재 많이 적용되어 지고 있는 Cap Sensor의 응용을 예로 들어 나타내었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.727-730
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• 2002

최근 키를 가지고 다니는 불편함과 보안성을 고려한 전자 키들이 많이 생산되고 있다. 키의 불편함과 보안성을 보완하는 방법에는 비밀번호 입력, 지문인식, 홍체인식 등의 방법이 이용되고 있는데, 본 논문에서는 비밀번호를 입력하는 방법으로 설계하였다. Altera사의 Software인 MAXPLUS II를 이용하여 설계하였고, Hardware Language인 VHDL을 이용하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1346-1355
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• 2005

Recently, the development of passive optical networks (PON) for FTTH (Fiber-To-The-Home) have been actively conducted. In PON, a burst-mode transceiver is one of key modules. In this paper, we have made the protype module of a 155.52 Mpbs optical burst-mode transceiver with commercially available chips and then have measured the performance. Also, a new method of burst-mode clock recovery have been proposed. The burst-mode clock recovery implemented by using CPLD(Complex Programmable Logic Device) has coupled with the above burst-mode transceiver and has been tasted.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.6
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• pp.550-559
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• 2005

The matrix converter provides sinusoidal input and output wave forms, bidirectional power flow, controllable input power factor and a long life, compared to the VSI(Voltage Source Inverter) with diode rectification stage at the input. However it has tasks, such as complexity of the control method, ride-through problem and low voltage-ratio limitation, to overcome for commercializing, This paper describes the design, construction and implementation of matrix converter based on space vector modulation technique. The implemented prototype of matrix converter is built using the exclusive IGBT module and control circuit constituted with DSP and CPLD and it has an input filter, overvoltage protection circuit and commutation means for overcoming practical issues. The good results tested using an induction motor are also presented.