• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.04b
• /
• pp.34-37
• /
• 2004

Recently advancing mobile communication tools and I.T industry, semiconductor device is requested more integrated, faster operation time and more scaled-down. Because of these reasons semiconductor device is requested multilayer interconnection. For the multilayer interconnection chemical mechanical polishing (CMP) becomes one of the most useful process in semiconductor manufacturing process. In this experiment, we focus on understand the characterize and improve the CMP technology by control of slurry flow rate. Consequently, we obtain that optimal flow rate of slurry is 170ml/min, since optimal conditions are less chemical flow and performance high with good selectivity to Ta. If we apply this results to copper CMP process. it is thought that we will be able to obtain better yield.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.11a
• /
• pp.147-150
• /
• 2002

In this study, we evaluated the dilute HF Cleaning to reduce residual defects made by W CMP process. But, One point we should focus is It should not effect to metal thin film reliability. The purpose of this test is to verify barrier metal damage during HF cleaning and based on this result we get rid of slurry residue defect which is main defect of W CMP process for the better yield.

• Journal of the Korean Society for Precision Engineering
• /
• v.21 no.11
• /
• pp.46-52
• /
• 2004

CMP (Chemical-Mechanical Polishing) is a process in which both chemical and mechanical mechanisms act simultaneously to produce the planarized wafer. CMP process is an extensive usage and continuing high growth rates in the semiconductor industry. The understanding of the process, however, is much slower. The nature of material removal from the wafer is still undefined and ambiguous. Material removal rate according to the slurry flow rate is also undefined and ambiguous. Thus, in this study, the basic mechanism of material removal rate as slurry flow rate is defined in terms of energy supply and energy loss.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.655-656
• /
• 2005

In the future, plastic based system will play a crucial role in modem life, for examples, transparent display or disposable electronics and so on. In this paper, we introduced a new method to fabricate the metal line on the plastic substrate. Metal lines were fabricated by hot embossing and CMP process on PMMA (polymethylmethacrylate) substrates. A Si mold was made by wet etching process and a PMMA wafer was cut off from I mm thick PMMA sheet. A 100 nm thick Al was deposited on PMMA wafers. The Al deposited PMMA wafer and the Si mold carefully sandwiched which was directly imprinted by hot embossing. After imprinting process, a residual Al layer was removed by CMP process. Finally, we found the entire process may be very useful to fabricate the metal line on plastic substrates.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.2
• /
• pp.47-51
• /
• 2013

Chemical mechanical polishing (CMP) has become one of the key processes in wafer level stacking technology for 3D stacked IC. In this study, two-step CMP process was proposed to polish $Cu/SiO_2$ hybrid bonding surface, that is, Cu CMP was followed by $SiO_2$ CMP to minimize Cu dishing. As a result, Cu dishing was reduced down to $100{\sim}200{\AA}$ after $SiO_2$ CMP and surface roughness was also improved. The bonding interface showed no noticeable dishing or interface line, implying high bonding strength.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.05d
• /
• pp.105-108
• /
• 2003

CMP(chemical mechanical polishing) process has been attracted as an essential technology of multi-level interconnection. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, slurry dominates more than 40 %. So, we focused how to reduce the consumption of raw slurry. In this paper, We have studied the CMP (chemical mechanical polishing) characteristics of slurry by adding of raw alumina abrasive and annealed alumina abrasive. As a experimental results, we obtained the comparable slurry characteristics compared with original silica slurry in the view point of high removal rate and low non-uniformity. Therefore, we can reduce the cost of consumables(COC) of CMP process for ULSI applications.

• Proceedings of the KIEE Conference
• /
• 2006.10a
• /
• pp.101-102
• /
• 2006

PZT thin films, which are the representative ferroelectric materials in ferroelectric random access memory (FRAM), have some serious problem such as the imprint, retention and fatigue which ferroelectric properties are degraded by repetitive polarization. BL T thin film capacitors were fabricated by plasma etching, however, the plasma etching of BLT thin film was known to be very difficult. In our previous study, the ferroelectric materials such as PZT and BLT were patterned by chemical mechanical polishing (CMP) using damascene process to top electrode/ferroelectric material/bottom electrode. It is also possible to pattern the BLT thin film capacitors by CMP, however, the CMP damage was not considered in the experiments. The properties of BLT thin films were changed by the change of polishing pressure although the removal rate was directly proportional to the polishing pressure in CMP process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.22 no.2
• /
• pp.114-118
• /
• 2009

PVA (polyvinyl alcohol) brush cleaning method is a typical cleaning method for semiconductor cleaning process especially post-CMP cleaning. PVA brush contacts with the wafer surface and abrasive particle, generating the contact rotational torque of the brush, which is the removal mechanism. The brush rotational torque can overcome theoretically the adhesion force generated between the abrasive particle and wafer by zeta potential. However, after CMP (chemical mechanical polishing) process, many particles remained on the wafer because the brush was contaminated in previous post-CMP cleaning step. The abrasive particle on the brush redeposits to the wafer. The level of the brush contamination increased according to the cleaning run time. After cleaning the brush, the level of wafer contamination dramatically decreased. Therefore, the brush cleanliness effect on the cleaning performance and it is important for the brush to be maintained clearly.

• Journal of the Korean Society for Precision Engineering
• /
• v.21 no.7
• /
• pp.22-29
• /
• 2004

As a result of high integration of semiconductor device, the global planarization of multi-layer structures is necessary. So the chemical mechanical polishing(CMP) is widely applied to manufacturing the dielectric layer and metal line in the semiconductor device. CMP process is under influence of polisher, pad, slurry, and process itself, etc. In comparison with the general CMP which uses the slurry including abrasives, fixed abrasive pad takes advantage of planarity, resulting from decreasing pattern selectivity and defects such as dishing & erosion due to the reduction of abrasive concentration especially. This paper introduces the manufacturing technique of fixed abrasive pad using hydrophilic polymers with swelling characteristic in water and explains the self-conditioning phenomenon. And the tungsten CMP using fixed abrasive pad achieved the good conclusion in terms of the removal rate, non-uniformity, surface roughness, material selectivity, micro-scratch free contemporary with the pad life-time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.125-126
• /
• 2005

Recently semiconductor devices are required more smaller scale and more powerful performance. For smaller scale of device, multilayer structure is proposed. And, for the higher performance, interconnection material is change to copper, because copper has high EM(Electro-migration)and low resistivity. Then copper CMP process is a great role in a multilayer formation of semiconductor. Copper process is different from aluminum process. ECP process is one of the copper processes. In this paper, we focused on the defects tendency by copper thickness which filled using ECP process. we observed hump high and dishing. Conclusively, hump hight reduced at copper thickness increased Also dishing reduced.