• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.140-143
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• 2003

BST thin films have a good thermal-chemical stability, insulating effect and variety of phases. However, BST thin films have problems of the aging effect and mismatch between the BST thin film and electrode. Also, due to the high defect density and surface roughness at grain boundarys and in the grains, which degrades the device performances. In order to overcome these weakness, we first applied the chemical mechanical polishing (CMP) process to the polishing of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. BST ferroelectric film was fabricated by the sol-gel method. And then, we compared the structural characteristics before and after CMP process of BST films. We expect that our results will be useful promise of global planarization for FRAM application in the near future.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.5
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• pp.976-985
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• 2002

The purpose of this paper is that the roughness(Rrms = 31$\AA$, Rp-v = 270$\AA$) of ITO thin film deposited by sputtering method for OELD is improved to Rrms $\leq$ 10$\AA$, Rp-v $\leq$ 80$\AA$ by chemical mechanical polishing(CMP). First, ITO thin films are polished with a variety of consumables (Pads, Slurries) to choose proper some for the roughness improvement and the CMP mechanism of ITO thin films is demonstrated on the ground of the experiment results. Henceforth, the CMP characteristics (Removal rate, Non-uniformity) of chosen consumables are evaluated according to processing conditions (Polishing pressures, Table velocities) and suitable conditions for ITO film CMP are selected. Finally, the electrical and optical properties (Sheet resistance, Transmittance) of ITO thin films are investigated to verify whether or not ITO thin film are still suitable for OELD after polished.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05d
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• pp.109-112
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• 2003

Recently, CMP (Chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of reused silica slurry in order to reduce the costs of CMP slurry. Also, we have collected the silica abrasive powders by filtering after subsequent CMP process for the purpose of abrasive particle recycling. And then, we annealed the collected abrasive powders to promote the mechanical strength of reduced abrasion force. Finally, we compared the CMP characteristics between self-developed KOH-based silica abrasive slurry and original slurry. As our experimental results, we obtained the comparable removal rate and good planarity with commercial products. Consequently, we can expect the saving of high cost slurry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.335-338
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• 2003

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-layer dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding $1\;{\mu}m$ in size, which could cause micro-scratch on the wafer surface. In this paper, we have studied aging effect the of CMP sin as a function of particle size. We prepared and compared the self-developed silica slurry by adding of abrasives before and after annealing. As our preliminary experiment results, we could be obtained the relatively stable slurry characteristics comparable to original silica slurry in the slurry aging effect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.4
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• pp.378-383
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• 2004

Tungsten is widely used as a plug for the multi-level interconnection structures. However, due to the poor adhesive properties of tungsten(W) on SiO$_2$ layer, the Ti/TiN barrier layer is usually deposited onto SiO$_2$ for increasing adhesion ability with W film. Generally, for the W-CMP(chemical mechanical polishing) process, the passivation layer on the tungsten surface during CMP plays an important role. In this paper, the effect of oxidant on the polishing selectivity of W/Ti/TiN layer was investigated. The alumina(A1$_2$O$_3$)-based slurry with $H_2O$$_2$ as the oxidizer was used for CMP applications. As an experimental result, for the case of 5 wt％ oxidizer added, the removal rates were improved and polishing selectivity of 1.4:1 was obtained. It was also found that the CMP characteristics of W and Ti metal layer including surface roughness were strongly dependent on the amounts of $H_2O$$_2$ oxidizer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1283-1287
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• 2004

The design rules are being more strict with requirement of operation speed and development of IC industry. For this reason, required minimum line-width has been narrowed under sub-micron region. As the length of minimum line-width is narrowed, local and global planarization are being prominent. CMP(Chemical-Mechanical Polishing), one of the planarizarion technology, is a process which polishes with the ascent of chemical reaction and relative velocity between pad and wafer without surface defects. CMP is performed with a complex interaction among many factors, how CMP has an interaction with such factors is not evident. Accordingly, the studies on this are still carrying out. Therefore, an examination of the CMP phenomena and an accurate understanding of compositive factors are urgently needed. In this paper, we will consider of the relations between the effects of temperature which influences many factors having an effect on polishing results and the characteristics of CMP in order to understand and estimate the influence of temperature. Then, through the interaction of shown temperature and polishing result, we could expect to boost fundamental understanding on complex CMP phenomena.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.113-113
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• 2008

Cu CMP (Chemical Mechanical Planarization) has been used to remove copper film and obtain a planar surface which is essential for the semiconductor devices. Generally, it is known that chemical reaction is a dominant factor in Cu CMP comparing to Silicon dioxide CMP. Therefore, Cu CMP slurry has been regarded as an important factor in the entire process. This investigation focused on understanding the effect of corrosion inhibitor on copper surface and CMP results. Benzotriazole (BTA) was used as a corrosion inhibitor in this experiment. For the surface analysis, electrochemical characteristics of Cu was measured by a potentiostat and surface modification was investigated by X-ray photoelectron spectroscopy (XPS). As a result, corrosion potential (Ecorr) increased and nitrogen concentration ratio on the copper surface also increased with BTA concentration. These results indicate that BTA prevents Cu surface from corrosion and forms Cu-BTA layer on Cu surface. CMP results are also well matched with these results. Material removal rate (MRR) decreased with BTA concentration and static etch rate also showed same trend. Consequently, adjustment of BTA concentration can give us control of step height variation and furthermore, this can be applicable for Cu pattern CMP.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.05a
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• pp.272-278
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• 2002

Recently, STI(Shallow Trench Isolation) process has attracted attention for high density of semiconductor device as a essential isolation technology. In this paper, the effect of pattern density, trench width and selectivity of slurry on dishing in STI CMP process was investigated by using specially designed isolation pattern. As trench width increased, the dishing tends to increase. At $20{\mu}m$ pattern size, the dishing was decreased with increasing pattern density Low selectivity slurry shows less dishing at over $160{\mu}m$ trench width, whereas high selectivity slurry shows less dishing at below $160{\mu}m$ trench width.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.378-379
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• 2006

CMP(chemical mechanical polishing) process has been attracted as an essential technology of multi-level interconnection. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, slurry dominates more than 40 %. So, we focused how to reduce the consumption of raw slurry. In this paper, $ZrO_2$, $CeO_2$, and $MnO_2$ abrasives were added de-ionized water (DIW) and pH control as a function of KOH contents. We have investigate the possibility of new abrasive for the oxide CMP application.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.935-938
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• 1997

Recently, the minimum line width shows a tendency to decrease and the multi-level increase in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as micro-scratches, abrasive contaminations, and non-uniformity of polished wafer edges. Wet etching include of Spin-etching can improve he defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(INterlayer-Dielectric) was removed by CMP and wet-etching methods in order to investigate the superiority of wet etching mechanism. In the thin film wafer, the results were evaluated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And pattern step height was also compared for planarization characteristics of the patterned wafer.