• Journal of Sensor Science and Technology
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• v.23 no.2
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• pp.87-93
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• 2014

In this paper, we propose a block-based low-power complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a simple pixel structure for power efficiency. This method, which uses an additional computation circuit, makes it possible to reduce the power consumption of the pixel array. In addition, the computation circuit for a block-based CIS is very flexible for various types of pixel structures. The proposed CIS was designed and fabricated using a standard CMOS 0.18 ${\mu}m$ process, and the performance of the fabricated chip was evaluated. From a resultant image, the proposed block-based CIS can calculate a differing contrast in the block and control the operating voltage of the unit blocks. Finally, we confirmed that the power consumption in the proposed CIS with a simple pixel structure can be reduced.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.388-396
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• 2012

In this paper, a $320{\times}240$ pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung $0.13{\mu}m$ 1P4M CMOS process and used a 4T APS with a pixel pitch of $2.25{\mu}m$. The measured column fixed pattern noise (FPN) is 0.10 LSB.

• Journal of Sensor Science and Technology
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• v.14 no.1
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• pp.28-32
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• 2005

In this paper, a CMOS integrated detection circuit for capacitive type fingerprint sensor signal processing is described. We designed a detection circuit of charge-sharing sensing scheme. The proposed detection circuit increases the voltage difference between a ridge and valley. The test chip is composed of $160{\times}192$ array sensing cells (12 by $12.7{\;}mm^{2}$). The chip was fabricated on a 0.35 m standard CMOS process. Measured difference voltage between a ridge and valley was 0.95 V.

• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.54-60
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• 1994

In this paper, the multi-sensor signal processing IC is designed. It consists of an analog multiplexer for selection of multi-sensor signals, active filters for noise rejection and signal amplification, and a sample and hold circuit for interface with digital signal processing. By implementing these circuits with CMOS transistors, integration, low power dissipation and miniaturization of the total signal processing system have been made possible.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.270-274
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• 2006

A color filter array (CFA) helps a single electrical image sensor to recognize color images. The Red-Green-Blue (RGB) Bayer CFA is commonly used, but the amount of the light which arrives at the photodiode is attenuated with this CFA. Red-White-Blue (RWB) CFA increases the amount of the light which arrives at photodiode by using White (W) pixels instead of Green (G) pixels. However, white pixels are saturated earlier than red and blue pixels. The pseudo multiple capture scheme and the corresponding RWB CFA were proposed to overcome the early saturation problem of W pixels. The prototype CMOS image sensor (CIS) was fabricated with $0.35-{\mu}m$ CMOS process. The proposed CIS solves the early saturation problem of W pixels and increases the dynamic range.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.11
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• pp.857-861
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• 2012

FPN (fixed-pattern-noise) mainly comes from the device or pattern mismatches in pixel and color filter, pixel photodiode leakage in CMOS image sensor. In this paper, optical stack module related pixel FPN was investigated and the classification of pixel FPN contribution with the individual optical module process was presented. The methodology and procedure would be helpful in reducing the greater pixel FPN and distinguishing the complex FPN sources with respect to various noise factors.

• Journal of Sensor Science and Technology
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• v.30 no.4
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• pp.223-228
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• 2021

This work presents a low-power CMOS image sensor (CIS) with a multi-column-parallel (MCP) readout structure while focusing on improving its performance compared to previous works. A delta readout scheme that utilizes the image characteristics is optimized for the MCP readout structure. By simply alternating the MCP readout direction for each row selection, additional memory for the row-to-row delta readout is not required, resulting in a reduced area of occupation compared to the previous work. In addition, the bias current of a pre-amplifier in a successive approximate register (SAR) analog-to-digital converter (ADC) changes according to the operating period to improve the power efficiency. The prototype CIS chip was fabricated using a 0.18-㎛ CMOS process. A 160 × 120 pixel array with 4.4 ㎛ pitch was implemented with a 10-bit SAR ADC. The prototype CIS demonstrated a frame rate of 120 fps with a total power consumption of 1.92 mW.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.38-45
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• 2007

A new 8-bit single-slope ADC using analog RAMP generator with digitally controllable dynamic range has been proposed and simulated for column level or per-pixel CMOS image sensor application. The conversion gain of ADC can he controlled easily by using frequency divider with digitally controllable diviber ratio, coarse/fine RAMP with class-AB op-amp, resistor strings, decoder, comparator, and etc. The chip area and power consumption can be decreased by simplified analog circuits and passive components. Proposed frequency divider has been implemented and verified with 0.65um, 2-poly, 2-metal standard CMOS process. And the functional verification has been simulated and accomplished in a 0.35$\mu$m standard CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.10
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• pp.2065-2067
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• 2015

In this paper, we analyze the performance of visible light communication system using rolling shutter CMOS sensor. For analysis, the effect of ISI (Inter-symbol Interference) on visible communication has been formulated. We validate our analysis through computer simulations.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.04a
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• pp.43-46
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• 2014

CMOS 이미지 센서는 모바일 디바이스, 특히 스마트 폰에 내장된 카메라에 가장 광범위하게 사용된다. 이러한 이미지 센서의 정상 동작을 검사하기 위해서는 불량화소 검출과 같은 테스트가 수행되어야 하며, 테스트를 위해서는 센서에 의해서 캡처된 이미지를 대상으로 이미지 처리를 할 수 있는 함수제공이 필수적이다. 이 논문에서는 CMOS 이미지 센서의 동작을 효율적이고 엄격하게 판단할 수 있는 자동 검사 시스템을 구축하고 이미지 센서로부터 캡처되는 이미지 데이터에 대해서 목적에 맞는 테스트를 수행 할 수 있도록 이미지 처리 함수를 구현하고 실험하였다.