• 센서학회지
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• 제23권2호
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• pp.87-93
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• 2014

In this paper, we propose a block-based low-power complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a simple pixel structure for power efficiency. This method, which uses an additional computation circuit, makes it possible to reduce the power consumption of the pixel array. In addition, the computation circuit for a block-based CIS is very flexible for various types of pixel structures. The proposed CIS was designed and fabricated using a standard CMOS 0.18 ${\mu}m$ process, and the performance of the fabricated chip was evaluated. From a resultant image, the proposed block-based CIS can calculate a differing contrast in the block and control the operating voltage of the unit blocks. Finally, we confirmed that the power consumption in the proposed CIS with a simple pixel structure can be reduced.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.388-396
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• 2012

In this paper, a $320{\times}240$ pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung $0.13{\mu}m$ 1P4M CMOS process and used a 4T APS with a pixel pitch of $2.25{\mu}m$. The measured column fixed pattern noise (FPN) is 0.10 LSB.

• 센서학회지
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• 제14권1호
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• pp.28-32
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• 2005

In this paper, a CMOS integrated detection circuit for capacitive type fingerprint sensor signal processing is described. We designed a detection circuit of charge-sharing sensing scheme. The proposed detection circuit increases the voltage difference between a ridge and valley. The test chip is composed of $160{\times}192$ array sensing cells (12 by $12.7{\;}mm^{2}$). The chip was fabricated on a 0.35 m standard CMOS process. Measured difference voltage between a ridge and valley was 0.95 V.

• 센서학회지
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• 제3권1호
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• pp.54-60
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• 1994

본 논문에서는 멀티센서 신호처리용 집적회로를 구성하였다. 제안된 회로는 멀티센서 신호 선택을 위한 아날로그 멀티플렉서, 노이즈 제거와 신호증폭을 위한 능동 필터, 디지탈 신호처리부와의 인터페이스를 위한 샘플-홀드 회로 등으로 구성하였다. 이러한 기능회로들을 CMOS 트랜지스터로 설계하여 집적화를 가능케 하였으며, 이로 인해 멀티센서 신호처리 시스템의 저소비전력화, 소형화를 구현케하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.270-274
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• 2006

A color filter array (CFA) helps a single electrical image sensor to recognize color images. The Red-Green-Blue (RGB) Bayer CFA is commonly used, but the amount of the light which arrives at the photodiode is attenuated with this CFA. Red-White-Blue (RWB) CFA increases the amount of the light which arrives at photodiode by using White (W) pixels instead of Green (G) pixels. However, white pixels are saturated earlier than red and blue pixels. The pseudo multiple capture scheme and the corresponding RWB CFA were proposed to overcome the early saturation problem of W pixels. The prototype CMOS image sensor (CIS) was fabricated with $0.35-{\mu}m$ CMOS process. The proposed CIS solves the early saturation problem of W pixels and increases the dynamic range.

• 한국전기전자재료학회논문지
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• 제25권11호
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• pp.857-861
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• 2012

FPN (fixed-pattern-noise) mainly comes from the device or pattern mismatches in pixel and color filter, pixel photodiode leakage in CMOS image sensor. In this paper, optical stack module related pixel FPN was investigated and the classification of pixel FPN contribution with the individual optical module process was presented. The methodology and procedure would be helpful in reducing the greater pixel FPN and distinguishing the complex FPN sources with respect to various noise factors.

• 센서학회지
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• 제30권4호
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• pp.223-228
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• 2021

This work presents a low-power CMOS image sensor (CIS) with a multi-column-parallel (MCP) readout structure while focusing on improving its performance compared to previous works. A delta readout scheme that utilizes the image characteristics is optimized for the MCP readout structure. By simply alternating the MCP readout direction for each row selection, additional memory for the row-to-row delta readout is not required, resulting in a reduced area of occupation compared to the previous work. In addition, the bias current of a pre-amplifier in a successive approximate register (SAR) analog-to-digital converter (ADC) changes according to the operating period to improve the power efficiency. The prototype CIS chip was fabricated using a 0.18-㎛ CMOS process. A 160 × 120 pixel array with 4.4 ㎛ pitch was implemented with a 10-bit SAR ADC. The prototype CIS demonstrated a frame rate of 120 fps with a total power consumption of 1.92 mW.

• 전기전자학회논문지
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• 제11권1호통권20호
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• pp.38-45
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• 2007

A new 8-bit single-slope ADC using analog RAMP generator with digitally controllable dynamic range has been proposed and simulated for column level or per-pixel CMOS image sensor application. The conversion gain of ADC can he controlled easily by using frequency divider with digitally controllable diviber ratio, coarse/fine RAMP with class-AB op-amp, resistor strings, decoder, comparator, and etc. The chip area and power consumption can be decreased by simplified analog circuits and passive components. Proposed frequency divider has been implemented and verified with 0.65um, 2-poly, 2-metal standard CMOS process. And the functional verification has been simulated and accomplished in a 0.35$\mu$m standard CMOS process.

• 한국통신학회논문지
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• 제40권10호
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• pp.2065-2067
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• 2015

본 논문에서는 Rolling Shutter CMOS 센서를 이용한 가시광 통신 시스템의 성능을 분석하였다. 성능분석을 위하여 ISI (Inter-symbol Interference)가 가시광통신에 미치는 영향을 분석하였다. 모의실험을 통하여 분석결과의 타당성을 검증하였다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2014년도 춘계학술발표대회
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• pp.43-46
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• 2014

CMOS 이미지 센서는 모바일 디바이스, 특히 스마트 폰에 내장된 카메라에 가장 광범위하게 사용된다. 이러한 이미지 센서의 정상 동작을 검사하기 위해서는 불량화소 검출과 같은 테스트가 수행되어야 하며, 테스트를 위해서는 센서에 의해서 캡처된 이미지를 대상으로 이미지 처리를 할 수 있는 함수제공이 필수적이다. 이 논문에서는 CMOS 이미지 센서의 동작을 효율적이고 엄격하게 판단할 수 있는 자동 검사 시스템을 구축하고 이미지 센서로부터 캡처되는 이미지 데이터에 대해서 목적에 맞는 테스트를 수행 할 수 있도록 이미지 처리 함수를 구현하고 실험하였다.