• Proceedings of the IEEK Conference
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.341-342
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• 2007

The IRFPA (InfraRed Focal Plane Array) ROIC (ReadOut Integrated Circuit) was designed in folded-cascode Op-Amp using $0.35{\mu}m$ CMOS technology. As the folded-cascode has high open-loop voltage gain and fast settling time, that used in many analog circuit designs. In this paper, folded-cascode Op-Amp for ROIC of the $32{\times}32$ IRFPA has been designed. HSPICE simulation results are unit gain bandwidth of 13.0MHz, 90.6 dB open loop gain, 8 V/${\mu}m$ slew rate, 600 ns settling time and $66^{\circ}$ phase margin.

• Journal of Sensor Science and Technology
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• 제32권6호
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• pp.432-440
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• 2023

This study introduces an efficient readout circuit designed for two-electrode electrocardiogram (ECG) recording, characterized by its low-noise and low-power consumption attributes. Unlike its three-electrode counterpart, the two-electrode ECG is susceptible to common-mode interference (CMI), causing signal distortion. To counter this, the proposed circuit integrates a common-mode charge pump (CMCP) with a window comparator, allowing for a CMI tolerance of up to 20 V_PP. The CMCP design prevents the activation of electrostatic discharge (ESD) diodes and becomes operational only when CMI surpasses the predetermined range set by the window comparator. This ensures power efficiency and minimizes intermodulation distortion (IMD) arising from switching noise. To maintain ECG signal accuracy, the circuit employs a chopper-stabilized instrumentation amplifier (IA) for low-noise attributes, and to achieve high input impedance, it incorporates a floating high-pass filter (HPF) and a current-feedback instrumentation amplifier (CFIA). This comprehensive design integrates various components, including a QRS peak detector and serial peripheral interface (SPI), into a single 0.18-㎛ CMOS chip occupying 0.54 mm². Experimental evaluations showed a 0.59 µV_RMS noise level within a 1-100 Hz bandwidth and a power draw of 23.83 µW at 1.8 V.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제39C권1호
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• pp.82-89
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• 2014

Recently, inertial sensors are popularly used for the location and position recognition of small devices for M2M/IoT. In this paper, we designed low power, low noise, small sized 6-axis inertial sensor IC for mobile applications, which uses a 3-axis piezo-electric gyroscope sensor and a 3-axis piezo-resistive accelerometer sensor. Proposed IC is composed of 3-axis gyroscope readout circuit, two gyroscope sensor driving circuits, 3-axis accelerometer readout circuit, 16bit sigma-delta ADC, digital filter and control circuit and memory. TSMC $0.18{\mu}m$ mixed signal CMOS process was used. Proposed IC reduces 27% of the current consumption of LSM330.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제23권2호
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• pp.89-92
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• 2010

A bolometer sensor used in an infrared thermal imaging system has many advantages on the process because it does not need a separate cooling system and its manufacturing is easy. However the sensitivity of the bolometer is low and the fixed pattern noise(FPN) is large, because the bolometer sensor is made by micro electro mechanical systems (MEMS). These problems can be fixed-by using the high performance readout integrated circuit(ROIC) with noise reduction techniques. In this paper, we propose differential delta sampling circuit to remove the mismatch noise of ROIC itself, the FPN of the bolometer. And for reduction of FPN noise, the reference signal compensation circuit which compensate the reference signal by using on-resistance of MOS transistor was proposed.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.563-564
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• 2006

A single photon counting type image sensor which is applicable for medical diagnosis with digitally obtained image and industrial purpose has been designed using $0.25{\mu}m$triple well CMOS process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.347-348
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• 2007

On-chip micro humidity sensor, using $CN_x$ films for the sensing material, was designed, simulated, and fabricated with Op amp based readout circuit and diode temperature sensors. To compensate the temperature and other gases, two methods were applied. One is wheatstone-bridge with reference FET that eliminates other undesirable chemical species, and the other is a diode temperature sensor to compensate the temperature effect. $CN_x$ film can be a new humidity sensing material, and has a strong potential to adapt to smart sensors or multi-sensors using MEMS or nano-technology. A particular design technology for integration of sensors and systems together was proposed that whole fabrication process could be achieved by a standard CMOS process.

• Journal of the Korea Institute of Military Science and Technology
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• 제10권2호
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• pp.152-159
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• 2007

This paper describes the design, fabrication, and measurement of ROIC(ReadOut Integrated Circuit) for $320{\times}256$ IRFPA(InfraRed Focal Plane Array). A ROIC plays an important role that transfer photocurrent generated in a detector device to thermal image system. Recently, the high performance and low power ROIC adding various functions is being required. According to this requirement, the design of ROIC focuses on 7MHz or more pixel rate, low power dissipation, anti-blooming, multi-channel output mode, image reversal, various windowing, and frame CDS(Correlated Double Sampling). The designed ROIC was fabricated using $0.6{\mu}m$ double-poly triple-metal Si CMOS process. ROIC function factors work normally, and the power dissipation of ROIC is 33mW and 90.5mW at 7.5MHz pixel rate in the 1-channel and 4-channel operation, respectively.

• Journal of Sensor Science and Technology
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• 제5권5호
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• pp.63-68
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• 1996

In order to implement the integrated capacitive pressure sensors, which contains integrated interface circuits to detect the electrical output signal, several main factors that have a bad effect on the characteristics of sensors must be improved, such as parasitic capacitance effects, temperature/thermal drift, and the leakage current of a readout circuitry. This paper describes the novel design of the dedicated CMOS readout circuitry that is consists of two capacitance to frequency converters and 4 bit digital logic compensating circuits. Dividing the oscillation frequency of a sensing sensor by that of reference sensor, this circuit is designed to eliminate the thermal/temperature drift and the effect of the leakage currents, and to access a digital signals to obtain a high signal-to-noise(S/N)ratio. Therefore, the resolution of this circuit can be increased by increasing the number of the digital bits. Digital compensated circuits of this circuits, except for the C-F converters, are fabricated on a FPGA chip, and fundamental performance of the circuits are evaluated.

• Journal of Sensor Science and Technology
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• 제25권5호
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• pp.349-353
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• 2016

Recently, research on bolometer-type uncooled infrared image sensor which is made for industrial applications has been increasing. In general, it is difficult to calibrate fixed pattern noise (FPN) of bolometer array. In this paper, average-current calibration algorithm is presented for reducing bolometer resistance offset. A resistor which is produced by standard CMOS process, on the average, has a deviation. We compensate for deviation of each resistor using average-current calibration algorithm. The proposed algorithm has been implemented by a chip which is consisted of a bolometer pixel array, average current generators, current-to-voltage converters (IVCs), a digital-to-analog converter (DAC), and analog-to-digital converters (ADCs). These bolometer-resistor array and readout circuit were designed and manufactured by $0.35{\mu}m$ standard CMOS process.

• Journal of Radiation Industry
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• 제6권1호
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• pp.31-40
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• 2012

There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.