• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.326-332
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• 2017

A switched VCO-based UWB transmitter for 3-5 GHz is implemented using $0.18{\mu}m$ CMOS technology. Using RF switch and timing control of DPGs, the uniform RF power and low power consumption are possible regardless of carrier frequency. And gate control of RF switch enables the undesired side lobe rejection sufficiently. The measured pulse width is tunable from 0.5 to 2 ns. The measured energy efficiency per pulse is 4.08% and the power consumption is 0.6 mW at 10 Mbps without the buffer amplifier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.3
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• pp.399-405
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• 2011

In this paper, we present the design of Q-band LC VCO and injection locking buffer for 77 GHz automotive radar sensor using 130 nm RF CMOS process. To improve the phase noise characteristic of LC tank, the transmission line is used. The negative resistance by the active device cross-coupled pair of buffer is used for high output power, with or without oscillation of buffer. The measured phase noise is -102 dBc/Hz at 1 MHz offset frequency and tuning range is 34.53~35.07 GHz. The output power is higher than 4.1 dBm over entire tuning range. The fabricated chip size is $510{\times}130\;um^2$. The power consumption of LC VCO is 10.8 mW and injection locking buffer is 50.4 mW from 1.2 V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.274-283
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• 2014

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved $f_tBV_{CEO}$ product (397 GHzV). As the $BV_{CEO}$ value is higher for low value of epi layer doping, higher supply voltage can be used to increase the $f_t$ value of the HBT. At 1.8 V $V_{CE}$, the $f_tBV_{CEO}$ product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV $f_tBV_{CEO}$ product at 1.2 V $V_{CE}$). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.1
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• pp.123-129
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• 2023

In this paper, the frequency synthesis(FS) MMIC and the receive MMICs were developed for a Ka-band compact radar. Also a compact Ka-band frequency synthesizer and a receiver were developed based on those MMICs. The FS MMIC and the wireless-receiver(WR) MMIC to receive the baseband frequency were manufactured by a 65 nm CMOS process and the front-end(FE) MMIC to receive the Ka-band frequency was manufactured by a 150 nm GaN process. Linear frequency modulation waveform and pulse waveform for the transmit signal were measured by output signal of frequency synthesizer. The measured performance of developed receiver including the FE MMICs and the WR MMIC were ≧ 80 dB gain, ≦ 6 dB noise figure and ≧ 10 dBm at OP1dB. The measurement results of the developed frequency synthesizer and the receiver including the manufactured MMICs showed that they could be applied to Ka-band compact radar.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.66-70
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• 2016

This paper presents an 24 GHz I/Q LO generator for a heartbeat measurement radar system. In order to improve the mismatch performance between I and Q LO signals against process variation, a 24 GHz I/Q LO generator employing a low-pass phase shifter and a high-pass phase shifter composed of inductors and capacitors is proposed. The proposed 24 GHz I/Q LO generator consists of an LO buffer, a low-pass phase shifter and a high-pass phase shifter. It was designed using a 65 nm CMOS technology and draws 8 mA from a 1 V supply voltage. The proposed 24 GHz I/Q LO generator shows a gain of 7.5 dB, a noise figure of 2.3 dB, 0.1 dB gain mismatch and $4.3^{\circ}$ phase mismatch between I and Q-path against process and temperature variations for the operating frequencies from 24.05 GHz to 24.25 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.9
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• pp.865-871
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• 2016

This work presents a radar signal interferer to be used for evaluating the mutual interference among automotive radars. The developed interfering signal generator is composed of a reference signal generator and a 77 GHz transmitter. Reference signal generator is made up of commercial chips and board, it can generate various modulated signal such as triangular wave, sawtooth wave and random frequency hopping. The transmitter generates 77 GHz band signal by multiplying modulated reference signal frequency 28 times. Transmitter was fabricated using 65 nm CMOS process, it can operate horn antenna by built in on-chip waveguide feeder. The transmitter exhibited 7.31~8.06 dBm output power over a frequency lock range of 75.6~77 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1228-1238
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• 2012

In this paper, we design, fabricate and measure two kinds of high-frequency packages for K-band CMOS FMCW radar chips using RF via structures. The packages are fabricated with the conventional PCB process and LTCC process. The design centering of the packages is performed at 24 GHz and impedance variation caused by the wire bonding and RF via structure is fully evaluated using 3D electromagnetic simulation. The RF via structure with characteristic impedance of $50{\Omega}$ is used to reduce impedance mismatch loss. Two kinds of test packages with back-to-back connected RF paths are fabricated and measured for the design verification of the PCB-based package and LTCC package. Their measured results show an insertion loss of less than 0.4 dB at 24 GHz and less than 0.5 dB for 20~29 GHz. The measured return loss is less than -13 dB for the PCB-based package and less than -15 dB for the LTCC package in the frequency band, but the return loss of the package itself is predicted to be better than that of the test package by about 5 dB, because the ripples of the back-to-back connection typically degrade the return loss by 5 dB or more.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.595-604
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• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.97-103
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• 2002

In this paper, a Logarithmic Video Amplifier(LVA) for radar system or satellite communications is described. The proposed LVA is composed of a input stage, amplification stage, and output stage. As well as a novel series-parallel architecture is proposed for the purpose of wide dynamic range and high speed operation, a newly developed input stage is designed in order to control the voltage level between LVA and detector diode. The LVA is fabricated with a 1.5um 2-poly 2-metal n-well Bi-CMOS technology, and the chip area is 1310 um x 1540 um. From the experimental results, it consumes 190 mW at 10V power supply, the chip has 60 dB dynamic range and 100ns falling time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.760-761
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• 2013

본 논문은 차량 추돌 예방 레이더용 24GHz 전압제어발진기를 제안한다. 이러한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정($f_T/f_{MAX}=120/140GHz$)으로 설계되어 있다. 이러한 회로는 스위치형 공진기 (switched resonator)의 기본 구조를 지닌 24GHz 주파수 대역을 사용할 수 있도록 CMOS LC 튜닝 회로를 포함하고 있다. 특히 전체 칩 면적을 줄이기 위해 수동형 인덕터 대신 능동형 인덕터부를 사용하였다. 본 연구에서 개발한 발진기는 전체 튜닝 범위에 대해 24GHz에서 8%의 측정결과를 보였으며, 600kHz 오프셋에서 24GHz에 대해 약 -89dBc/Hz의 우수한 위상 잡음 특성을 보였다.