• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.40-47
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• 2007

For image processing hardware, including a face detecting engine, efficient constitution of external and internal memories is a consequential point because huge memory is required to store various signal processing filters and incoming images. In this paper, we modified a face detect algerian of a general filter method for efficient hardware design. In the hardware, several memory design techniques are presented for efficient handling of image data : re-accessing avoidance with minimized internal memory usage, residing frequently accessed memory and sequence memory accessing. The hardware which can process 25 frame image data per one second with 40KB internal memory was verified by using ARM(S3C2440A) and Virtex4 FPGA and it is being fabricated as a ASIC chip using Samsung CMOS 0.18um technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• Journal of IKEEE
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• v.17 no.1
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• pp.77-82
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• 2013

In this paper, dc-dc buck converter controled by the peak current-mode pulse-width-modulation (PWM) presented. Based on the small-signal model, we propose the novel methods of the power stage and the systematic stability designs. To improve the reliability and performance, over-temperature and over-current protection circuits have been designed in the dc-dc converter systems. To prevent electrostatic An electrostatic discharge (ESD) protection circuit is proposed. The proposed dc-dc converter circuit exhibits low triggering voltage by using the gate-substrate biasing techniques. Throughout the circuit simulation, it confirms that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS (8.2V). The circuit simulation is performed by Mathlab and HSPICE programs utilizing the 0.35um BCD (Bipolar-CMOS-DMOS) process parameters.

• Journal of IKEEE
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• v.21 no.1
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• pp.66-69
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• 2017

In recent year, energy harvesting technologies from the ambient environments such as light, motion, wireless waves, and temperature again a lot of attraction form research community [1-5] due to its efficient solution in order to substitute for conventional power delivery methods, especially in wearable together with on-body applications. The drawbacks of battery-powered characteristic used in commodity applications lead to self-powered, long-lifetime circuit design. Thermoelectric generator, a solid-state sensor, is useful compared to the harvesting devices in order to enable self-sustained low-power applications. TEG based on the Seebeck effect is utilized to transfer thermal energy which is available with a temperature gradient into useful electrical energy. Depending on the temperature difference between two sides, amount of output power will be proportionally delivered. In this work, we illustrated a low-input voltage energy harvesting circuit applied discontinuous conduction mode (DCM) method for getting an adequate amount of energy from thermoelectric generator (TEG) for a specific wearable application. With a small temperature gradient harvested from human skin, the input voltage from the transducer is as low as 60mV, the proposed circuit, fabricated in a $0.6{\mu}m$ CMOS process, is capable of generating a regulated output voltage of 4.2V with an output power reaching to $40{\mu}W$. The proposed circuit is useful for powering energy to battery-less systems, such as wearable application devices.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.22.2-22.2
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• 2009

Currently, metal silicides become increasingly more essential part as a contact material in complimentary metal-oxide-semiconductor (CMOS). Among various silicides, NiSi has several advantages such as low resistivity against narrow line width and low Si consumption. Generally, metal silicides are formed through physical vapor deposition (PVD) of metal film, followed by annealing. Nanoscale devices require formation of contact in the inside of deep contact holes, especially for memory device. However, PVD may suffer from poor conformality in deep contact holes. Therefore, Atomic layer deposition (ALD) can be a promising method since it can produce thin films with excellent conformality and atomic scale thickness controllability through the self-saturated surface reaction. In this study, Ni thin films were deposited by thermal ALD using bis(dimethylamino-2-methyl-2-butoxo)nickel [Ni(dmamb)2] as a precursor and NH3 gas as a reactant. The Ni ALD produced pure metallic Ni films with low resistivity of 25 $\mu{\Omega}cm$. In addition, it showed the excellent conformality in nanoscale contact holes as well as on Si nanowires. Meanwhile, the Ni ALD was applied to area-selective ALD using octadecyltrichlorosilane (OTS) self-assembled monolayer as a blocking layer. Due to the differences of the nucleation on OTS modified surfaces toward ALD reaction, ALD Ni films were selectively deposited on un-coated OTS region, producing 3 ${\mu}m$-width Ni line patterns without expensive patterning process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.91-96
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• 1992

The nonvolatile SNOSFET EEPROM memory devices with the channel width and iength of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] were fabricated by using the actual CMOS 1 [Mbit] process technology. The charateristics of I$\_$D/-V$\_$D/, I$\_$D/-V$\_$G/ were investigated and compared with the channel width and length. From the result of measuring the I$\_$D/-V$\_$D/ charges into the nitride layer by applying the gate voltage, these devices ere found to have a low conductance state with little drain current and a high conductance state with much drain current. It was shown that the devices of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$] represented the long channel characteristics and the devices of 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] represented the short channel characteristics. In the characteristics of I$\_$D/-V$\_$D/, the critical threshold voltages of the devices were V$\_$w/ = +34[V] at t$\_$w/ = 50[sec] in the low conductance state, and the memory window sizes wee 6.3[V], 7.4[V] and 3.4[V] at the channel width and length of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$], 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$], respectively. The positive logic conductive characteristics are suitable to the logic circuit designing.

• Journal of Sensor Science and Technology
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• v.19 no.4
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• pp.306-312
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• 2010

We have detected deoxynivalenol(DON) using a metal-oxide-semiconductor field-effect-transistor(MOSFET)-based biosensor. The MOSFET-based biosensor is fabricated by a standard complementary metal-oxide-semiconductor(CMOS) process, and the biosensor's electrical characteristics were investigated. The output of the sensor was stabilized by employing a reference electrode that applies a fixed bias to the gate. Au which has a chemical affinity for thiol was used as the gate metal to immobilize a self-assembled monolayer(SAM) made of 16-mercaptohexadecanoic acid(MHDA). The SAM was used to immobilize anti-deoxynivalenol antibody. The carboxyl group of the SAM was bound to the anti- deoxynivalenol antibody. Anti-deoxynivalenol antibody and deoxynivalenol were bound by an antigen-antibody reaction. In this study, it is confirmed that the MOSFET-based biosensor can detect deoxynivalenol at concentrations as low as 0.1 ${\mu}g$/ml. The measurements were performed in phosphate buffered saline(PBS; pH 7.4) solution. To verify the interaction among the SAM, antibody, and antigen, surface plasmon resonance(SPR) measurements were performed.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1268-1270
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• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.214.2-214.2
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• 2013

Device performance for the 45 and 32 nm node CMOS technology requires the integration of ultralow-k materials. To lower the dielectric constant for PECVD and spin-on materials, partial replacement of the solid network with air (k=1.01) appears to be more intuitive and direct option. This can be achieved introducting of second "labile" phase during depositoin that is removed during a subsequent UV curing and annealing step. Besides, with shrinking line dimensions the resistivity of barrier films cannot meet the International Technology Roadmap for Semiconductors (ITRS) requirements. To solve this issue self-forming diffusion barriers have drawn attention for great potential technique in meeting all ITRS requirments. In this present work, we report a Cu-V alloy as a materials for the self-forming barrier process. And we investigated diffusion barrier properties of self-formed layer on low-k dielectrics with or without UV curing treatment. Cu alloy films were directly deposited onto low-k dielectrics by co-sputtering, followed by annealing at various temperatures. X-ray diffraction revealed Cu (111), Cu (200) and Cu (220) peaks for both of Cu alloys. The self-formed layers were investigated by transmission electron microscopy. In order to compare barrier properties between V-based interlayer on low-k dielectric with UV curing and interlayer on low-k dielectric without UV curing, thermal stability was measured with various heat treatment temperature. X-ray photoelectron spectroscopy analysis showed that chemical compositions of self-formed layer. The compositions of the V based self-formed barriers after annealing were strongly dominated by the O concentration in the dielectric layers.

• Current Optics and Photonics
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• v.2 no.5
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• pp.422-430
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• 2018

Rolling shutter operation of CMOS cameras can be utilized in optical camera communications in order to transmit data from an LED to mobile devices such as smart-phones. From temporally modulated light, a spatial flicker pattern is obtained in the captured image, and this is used for signal recovery. Due to the degradation of rolling shutter images caused by light smear, motion blur, and focus blur, the conventional decoding schemes for rolling shutter cameras based on the pattern width for 'OFF' and 'ON' cannot guarantee robust communications performance for practical uses. Aside from conventional techniques, such as polynomial fitting, histogram equalization can be used for blurry light mitigation, but it requires additional computation abilities resulting in burdens on mobile devices. This paper proposes a transition-based decoding scheme for rolling shutter cameras in order to offer simple and robust data decoding in the presence of image degradation. Based on the designed synchronization pulse and modulated data symbols according to the LED dimming level, the decoding process is conducted by observing the transition patterns of two sequential symbol pulses. For this, the extended symbol pulse caused by consecutive symbol pulses with the same level determines whether the second pulse should be included for the next bit decoding or not. The proposed method simply identifies the transition patterns of sequential symbol pulses other than the pattern width of 'OFF' and 'ON' for data decoding, and thus, it is simpler and more accurate. Experimental results ensured that the transition-based decoding scheme is robust even in the presence of blurry lights in the captured image at various dimming levels