• 한국전기전자재료학회논문지
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• 제29권12호
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• pp.750-758
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• 2016

For the channel doping of shallow junction and retrograde well formation in CMOS, indium can be implanted in silicon. The retrograde doping profiles can serve the needs of channel engineering in deep MOS devices for punch-through suppression and threshold voltage control. Indium is heavier element than B, $BF_2$ and Ga ions. It also has low coefficient of diffusion at high temperatures. Indium ions can be cause the erode of wafer surface during the implantation process due to sputtering. For the ultra shallow junction, indium ions can be implanted for p-doping in silicon. UT-MARLOWE and SRIM as Monte carlo ion-implant models have been developed for indium implantation into single crystal and amorphous silicon, respectively. An analytical tool was used to carry out for the annealing process from the extracted simulation data. For the 1D (one-dimensional) and 2D (two-dimensional) diffused profiles, the analytical model is also developed a simulation program with $C^{{+}{+}}$ code. It is very useful to simulate the indium profiles in implanted and annealed silicon autonomously. The fundamental ion-solid interactions and sputtering effects of ion implantation are discussed and explained using SRIM and T-dyn programs. The exact control of indium doping profiles can be suggested as a future technology for the extreme shallow junction in the fabrication process of integrated circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권3호
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• pp.198-206
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• 2011

This paper presents a new programmable compensation circuit (PCC) for a System-on-Chip (SoC). The PCC is integrated with $0.18-{\mu}m$ BiCMOS SiGe technology. It consists of RF Design-for-Testability (DFT) circuit, Resistor Array Bank (RAB) and digital signal processor (DSP). To verify performance of the PCC we built a 5-GHz low noise amplifier (LNA) with an on-chip RAB using the same technology. Proposed circuit helps it to provide DC output voltages, hence, making the RF system chain automatic. It automatically adjusts performance of an LNA with the processor in the SoC when it goes out of the normal range of operation. The PCC also compensates abnormal operation due to the unusual PVT (Process, Voltage and Thermal) variations in RF circuits.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.629-632
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• 1998

This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.

• 대한전자공학회논문지
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• 제27권12호
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• pp.1870-1877
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• 1990

The electromagnetic properties of P- and n-channel split drain magnetic sensitive MOSFET fabricated using 2\ulcorner design rules and CMOS process technology has been investigated. The achieved output voltage in the double drain MOSFET was 160mV at 10\ulcorner drain current and magnetic flux density of 10kG, and the sensitivity was 1.6x10**3 V/A\ulcornerG. A further higher sensitivity was obtained by introducing a third drain in the split region. In this case, the triple drain MOSFET showed a much higher sensitivity of 2x10**3 V/A\ulcornerG under the same condition. Also, the linearity of output voltage vs. magnetic flux density was excellent.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.158.1-158
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• 2001

An algorithmic gray code analog-to-digital converter (ADC), which is based on gray coding, is proposed in this article. The realization method makes use of a MOS triangular function circuit to provide a high-speed operation and low accumulated error. The proposed ADC is simple, small in size and suitable for fabrication using a standard CMOS process. Simulation results showing the performances of the proposed circuit are also included.

• 대한전자공학회논문지
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• 제25권6호
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• pp.700-709
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• 1988

A new technique is proposed for switch-level logic simulation for NMOS and CMOS logic circuits. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance and the device configuration ratio, the polynomial coefficients being so determined as to best fit the SPICE simuladtion results for a given fabrication process. This approach can easily and accurately be extened to the case of multiple input transitions. The simulation results show that proposed method can predict the delay times within 5% error and with a speed up by a factor of three orders of magnitude for several circuits tested, as compared with the SPICE simulation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 추계학술대회 논문집
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• pp.14-17
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• 1992

To analyze Nonvolatile SNOSFET(polySilicon-Nitride-Oxide-Semiconductor Field Effect Transistor) memory device, two dimensional numerical computer simulation program was developed. The equation discretization was performed by the Finite difference method and the solution was derived by the Iteration method. The doping profile of n-channel device which was fabricated by 1Mbit CMOS process was observed. The electrical potential and the carrier concentration distribution to applied bias condition were observed in the inner of a device. As a result of the write and the erase to memory charge quantity, the threshold voltage shift is expected. Therefore, without device fabrication, the operating characteristics of the device was observed under various the processing and the operating condition.

• Journal of Power Electronics
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• 제17권5호
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• pp.1372-1381
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• 2017

This paper presents a high-side switch driver IC capable of improving the current sensing accuracy and providing reverse battery protection. Power semiconductor switches used to replace relay switches are encumbered by two disadvantages: they are prone to current sensing errors and they require additional external protection circuits for reverse battery protection. The proposed IC integrates a gate driver and current sensing blocks, thus compensating for these two disadvantages with a single IC. A p-sub-based 90-V $0.13-{\mu}m$ bipolar-CMOS-DMOS (BCD) process is used for the design and fabrication of the proposed IC. The current sensing accuracy (error ${\leq}{\pm}5%$ in the range of 0.1 A-6.5 A) and the reverse battery protection features of the proposed IC were experimentally tested and verified.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권9호
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• pp.650-656
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• 2004

This paper presents block and timing diagrams of the DWA(data weighted averaging) to optimize a feedback time delay of the sigma-delta modulator. Through the Matlab modeling, the optimized coefficients of the integrators are obtained to design the modulator. And then the fully differential SC integrators, feedback DAC, 9-level quantizer, and DWA are designed by considering the nonideal characteristics of the modulator. The designed second-order multibit modulator is fabricated in a 0.35$\mu\textrm{m}$ CMOS process. The designed modulator achieves 73dB signal-to-noise ratio and 72dB dynamic range at 1.2Vp-p 585kHz input singal and 52.8MHz sampling frequency.

• The Korean Journal of Ceramics
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• 제3권1호
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• pp.18-20
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• 1997

The fabrication process of silicon-diamond(SOD) structure wafer were studied. Microwave plasma chemical vapor deposition (MWPCVD) and annealing technology were used to synthesize diamond film with high resistivity and thermal conductivity. Bonding and etchback silicon-on-diamond (BESOD) were utilized to form supporting substrate and single silicon thin layer of SOD wafer. At last, a SOD structure wafer with 0.3~1$\mu\textrm{m}$ silicon film and 2$\mu\textrm{m}$ diamond film was prepared. The characteristics of radiation for a CMOS integrated circuit (IC) fabricated by SOD wafer were studied.