• 센서학회지
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• 제27권6호
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• pp.362-367
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• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

• 센서학회지
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• 제30권5호
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• pp.295-299
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• 2021

In this study, we present a complementary metal-oxide-semiconductor (CMOS) binary image sensor. It can shoot an object rotating at a high-speed by using a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector. The GBT PMOSFET-type photodetector amplifies the photocurrent generated by light. Therefore, it is more sensitive than a standard N+/P-substrate photodetector. A binary operation is installed in a GBT PMOSFET-type photodetector with high-sensitivity characteristics, and the high-speed operation is verified by the output image. The binary operations circuit comprise a comparator and memory of 1- bit. Thus, the binary CMOS image sensor does not require an additional analog-to-digital converter. The binary CMOS image sensor is manufactured using a standard CMOS process, and its high- speed operation is verified experimentally.

• 센서학회지
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• 제30권2호
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• pp.82-87
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• 2021

In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.

• 센서학회지
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• 제30권1호
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• pp.61-65
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• 2021

In this study, we propose a 2500 frame per second (fps) high-speed binary complementary metal oxide semiconductor (CMOS) image sensor using a gate/body-tied (GBT) p-channel metal oxide semiconductor field effect transistor-type high-speed photodetector. The GBT photodetector generates a photocurrent that is several hundred times larger than that of a conventional N+/P-substrate photodetector. By implementing an additional binary operation for the GBT photodetector with such high-sensitivity characteristics, a high-speed operation of approximately 2500 fps was confirmed through the output image. The circuit for binary operation was designed with a comparator and 1-bit memory. Therefore, the proposed binary CMOS image sensor does not require an additional analog-to-digital converter (ADC). The proposed 2500 fps high-speed operation binary CMOS image sensor was fabricated and measured using standard CMOS process.

• 센서학회지
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• 제29권2호
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• pp.82-88
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• 2020

In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for high-speed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 ㎛ CMOS process.

• 센서학회지
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• 제23권5호
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• pp.332-336
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• 2014

In this paper, we propose a complementary metal oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) PMOSFET-type photodetector for high-speed operation. The GBT photodetector of an active pixel sensor (APS) consists of a floating gate ($n^+$-polysilicon) tied to the body (n-well) of the PMOSFET. The p-n junction photodiode that is used in a conventional APS has a good dynamic range but low photosensitivity. On the other hand, a high-gain GBT photodetector has a high level of photosensitivity but a narrow dynamic range. In addition, the pixel size of the GBT photodetector APS is less than that of the conventional photodiode APS because of its use of a PMOSFET-type photodetector, enabling increased image resolution. A CMOS binary image sensor can be designed with simple circuits, as a complex analog to digital converter (ADC) is not required for binary processing. Because of this feature, the binary image sensor has low power consumption and high speed, with the ability to switch back and forth between a binary mode and an analog mode. The proposed CMOS binary image sensor was simulated and designed using a standard CMOS $0.18{\mu}m$ process.

• 제어로봇시스템학회논문지
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• 제14권8호
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• pp.767-773
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• 2008

This paper presents a localization system based on the use of electric compass and tracking IR light source. Digital RGB(Red, Green, Blue)signal of digital CMOS Camera is sent to CPLD which converts the color image to binary image at 30 frames per second. CMOS camera has IR filter and UV filter in front of CMOS cell. The filters cut off above 720nm light source. Binary output data of CPLD is sent to DSP that rapidly tracks the IR light source by moving Camera tilt DC motor. At a robot toward north, electric compass signals and IR light source angles which are used for calculating the data of the location system. Because geomagnetic field is linear in local position, this location system is possible. Finally, it is shown that position error is within ${\pm}1.3cm$ in this system.

• 한국정보통신학회논문지
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• 제15권11호
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• pp.2365-2373
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• 2011

본 논문은 고속화, 소형화 및 저전력을 요구하는 모바일 기기 및 디지털 카메라에 알맞은 실시간 얼굴 검출 하드웨어 IP(Intellectual Property)를 제안한다. 제안한 얼굴 검출 시스템은 검출 성능의 주요 원인인 조명 변화나 얼굴 크기, 다양한 얼굴 각도에 강인한 얼굴 검출을 수행한다. 입력 영상에 대해 조명 변화에 강인한 특성을 가지는 LBP(Local Binary Pattern) 변환을 거치고 Adaboost 알고리즘을 이용하여 다양한 얼굴 각도에 대해 미리 학습시킨 얼굴 특징 정보를 바탕으로 얼굴을 검출한다. 입력 영상 QVGA($320{\times}240$) 크기에서 최대 36개의 얼굴 검출 가능하며 Verilog-HDL을 사용하여 하드웨어로 설계하였다. 또한 FPGA 검증을 위해 Xilinx사의 Virtex5 XC5VLX330 FPGA 보드와 HD급 CMOS 이미지 센서(CIS)를 사용하여 하드웨어 구현을 검증하였다.

• 한국정보통신학회논문지
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• 제18권3호
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• pp.643-650
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• 2014

TOF(Time-Of-Flight) 센서에 의해 획득된 정보로부터 3차원 깊이 영상(depth image)을 추출하기 위한 위상 연산기 하드웨어를 구현한다. 설계된 위상 연산기는 DCORDIC(Differential COordinate Rotation DIgital Computer) 알고리듬의 벡터링 모드를 이용하여 아크탄젠트 연산을 수행하며, 처리량과 속도를 늘리기 위해 잉여 이진 수체계와 파이프라인 구조를 적용하였다. 고정 소수점 MATLAB 시뮬레이션을 통해 검증하고 최적 데이터 비트 수 및 반복 횟수를 결정하였으며, MATLAB/Simulink와 FPGA 연동을 통해 하드웨어 동작을 검증하였다. TSMC $0.18-{\mu}m$ CMOS 공정으로 테스트 칩을 제작하였으며, 테스트 결과 정상 동작함을 확인하였다. 약 82,000 게이트로 구현되었고, 400MHz@1.8V로 동작하여 400 MS/s의 연산 성능을 갖는 것으로 평가되었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.494-496
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• 2002

A bi-directional and multi-channel wireless telemetry capsule, 11mm in diameter, is presented that can transmit video images from inside the human body and receive a control signal from an external control unit. The proposed telemetry capsule includes transmitting and receiving antennas, a demodulator, decoder, four LEDs, and CMOS image sensor, along with their driving circuits. The receiver demodulates the received signal radiated from the external control unit. Next, the decoder receives the stream of control signals and interprets five of the binary digits as an address code. Thereafter, the remaining signal is interpreted as four bits of binary data. Consequently, the proposed telemetry module can demodulate external signals so as to control the behavior of the camera and four LEDs during the transmission of video images. The proposed telemetry capsule can simultaneously transmit a video signal and receive a control signal determining the behavior of the capsule itself. As a result, the total power consumption of the telemetry capsule can be reduced by turning off the camera power during dead time and separately controlling the LEDs for proper illumination of the intestine.