• Journal of the Semiconductor & Display Technology
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• v.2 no.1
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• pp.11-14
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• 2003

The high Q(quality factor) suspended spiral inductors were fabricated on the silicon substrate by 3D surface micromachined process. The integration of 2.4GHz VCO has been performed by fabricating suspended spiral inductor of the top of CMOS VCO circuit. The phase noise of VCO integrated MEMS inductor is 93.5 dBc/Hz at 100kHz of offset frequency.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.98-106
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• 1994

To realize high accuracy and high speed we developed a new self compensation scheme and applied it to a 10-bit D/A converter. This circuit can compensate the device mismatch without interrupting the D/A converter operation. With the compensation circuit,INA decreased down to 0.22LSB from 0.47LSB. The device was fabricated using a 0.8$\mu$m CMOS process. The area of the D/A converter core is 3.2mm$^{2}$ and the area of the compensation part is 0.64mm$^{2}$.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.563-564
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• 2006

A single photon counting type image sensor which is applicable for medical diagnosis with digitally obtained image and industrial purpose has been designed using $0.25{\mu}m$triple well CMOS process.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.519-520
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• 2006

In this paper, we propose a voltage-controlled ring oscillator (VCO) for a 900 MHz low-noise fractional-N frequency synthesizer. The VCO delay cell is based on an nMOS source-coupled pair with load elements [1] and a combined tail current sources which consist of a large and a small current source to control the integer and fractional behaviors, respectively. The Spectre simulation results of the scheme in a 0.18um CMOS process show the accurate control of the KVCO better than the conventional one.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.511-512
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• 2006

Three stage(CIC-FIR-FIR) decimation filter in delta-sigma A/D converter for audio is designed. A canonical signed digit(CSD) code method is used to minimize area of multipliers. This filter is designed in 0.25um CMOS process and incorporates $1.36\;mm^2$ of active area. Measured results show that this decimation filter is suitable for digital audio A/D converters.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.983-984
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• 2006

Multi-band VCO with fast response adaptive frequency calibration (AFC) technique is designed in 1.8V $0.18{\mu}m$ CMOS process. The possible operation is verified for 5.8GHz band, 5.2GHz band, and 2.4GHz band using the switchable L-C resonators for 802.11a/b/g WLAN applications. To linearize its frequency-voltage gain, optimized multiple MOS varactor biasing technique is used. In order to operate in each band frequency range with reduced VCO gain, 4-bit digitally controlled switched-capacitor bank is used and a wide-range digital logic quadricorrelator is implemented for fast frequency detector.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.520-527
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• 2016

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.488-496
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• 2016

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.375-379
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• 2016

A current subtraction technique with parallel operation system is proposed to remove excessive current in touch screen application. The proposed current subtraction remove the current which go into the input node of charge amplifier. The value of subtraction current is same with current when touch screen is not touched. As a result, charge amplifier output is only proportional to variation of mutual capacitor, which make dynamic rage is increased. Also, Transmitter (Tx) driving signal and subtraction driving signal are out of phase each other. Thus, noise generated in Tx is cancelled. The proposed IC is implemented in a mixed-mode 0.18-um CMOS process. Overall system is designed for touch screen panel (TSP) with 16 driving lines and 8 sensing lines. 5-V supply voltages are used in the proposed circuits. For multiple Tx driving signal, Walsh codes are used and signal frequency is 300 khz. By using proposed technique, dynamic rage is improved 36 dB.