• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.585-586
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• 2008

In this paper, a novel beta-multiplier reference current source circuit for the 800mV power-supply voltage is presented. In order to cope with the narrow input common-mode range of the OpAmp in the reference circuit, shunt resistive voltage divider branches were deployed. High gain OpAmp was designed to compensate intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18um CMOS process with nominal Vth of 420mV and -450mV for nMOS and pMOS transistor respectively. The total power consumption including OpAmp is less than 50uW.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.599-600
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• 2008

This paper presents a high performance DC-DC boost converter by current-mode control method. As load current change, the converter change PWM/PFM operation automatically. current-mode DC-DC boost converter is implemented in a standard $0.35{\mu}m$ CMOS process. The peak efficiency was 94 % with a switching frequency of 1.2MHz.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.158.1-158
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• 2001

An algorithmic gray code analog-to-digital converter (ADC), which is based on gray coding, is proposed in this article. The realization method makes use of a MOS triangular function circuit to provide a high-speed operation and low accumulated error. The proposed ADC is simple, small in size and suitable for fabrication using a standard CMOS process. Simulation results showing the performances of the proposed circuit are also included.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1192-1195
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• 2002

In this paper, we propose Low-Power Receiver circuits for a wireless communication system using ASK signal. Their structures are suitable for low supply current. The proposed circuits are designed and simulated by Spectre using 0.8m CMOS process parameters, and operate with supply current below 1.5${\mu}\textrm{A}$.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.759-762
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• 2002

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOS-FET (FG-MOSFET) is proposed. The proposed-circuit is the grounded VCLVR consists of only an ordinary MOSFET and an FG-MOSFET. The advantage of the proposed VCLVR are low-voltage and wide-input range. Next, as applications, a floating-node voltage controlled variable resistor and an operational transconductance amplifier using the proposed VCLVRs are proposed. The performance of the proposed circuits are characterized through HSPICE simulations with a standard 0.6 ${\mu}$m CMOS process. simulations of the proposed VCLVR demonstrate a resistance value of 40 k$\Omega$ to 338 k$\Omega$ and a THD of less than 1.1 %.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.160-163
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• 2000

In this paper, we propose an efficient technique to minimize the input offset of a dynamic latch comparator. We analyzed offset due to charge injection mismatching and unwanted positive feedback during sampling phase. The last one was only considered in the previous works. Based on the analysis, we proposed a modified dynamic latch with initialization switch. The proposed circuit was simulated using 0.65$\mu\textrm{m}$ CMOS process parameter with 5v supply. The simulation results showed that the input offset is less than 5mv at 200㎒ sampling frequency and the input offset is improved about 80% compared with previous work in 5k$\Omega$ input resistance.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.156-159
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• 2000

This paper presents a low-voltage, low-power $\Sigma$Δ modulator for audio applications. It use a simple second-order fully-differential switched-capacitor structure with a sampling frequency of 12.5 MHz and oversampling ratio of 256. It operates from a single 1.5V Bower supply and dissipates 2 ㎽. Extensive simulations using 0.25 ${\mu}{\textrm}{m}$ CMOS Process parameters show that it achieves 96㏈ peak SNDR in a 22 KHz bandwidth.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.919-922
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• 2003

This paper presents a novel low power driving circuit for passive matrix organic lighting emitting diodes (OLED) displays. The proposed driving method for a low power OLED driving circuit which reduce large parasitic capacitance in OLED panel only use current driving method, instead of mixed mode driving method which uses voltage pre-charge technique. The driving circuit is implemented to one chip using 0.35${\mu}{\textrm}{m}$ CMOS process with 18V high voltage devices and it is applicable to 96(R.G.B)X64, 65K color OLED displays for mobile phone application. The maximum switching power dissipation of driving power dissipation is 5.7mW and it is 4% of that of the conventional driving circuit.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.887-890
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• 2003

High Speed data transmission over a long length of cable is limited due to the limited bandwidth of a cable which introduces ISI(Inter Symbol Interference). In order to compensate for the loss and phase dispersion in the cable, a pulse shaping in a transmitter and a line equalizer in receiver can be used. This paper presents a low-power and small-ana analog adaptive pulse shaping circuit and line equalizer, The design was fabricated in a 0.25${\mu}{\textrm}{m}$ mixed-signal CMOS process. The proposed pulse shaping circuit and equalizer operate at 400Mb/s on 50m STP(Shielded Twisted Pair) cable. It consumes 28.5${\mu}{\textrm}{m}$ with a 2.5-V power supply and occupies only 0.098 $\textrm{mm}^2$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.131-139
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• 1996

Inthis apper wa analyzed the channel-hot-electron programming characteristics of the single-poly EEPROM with different control gate and drain structures. The single-poly EEPROM uses the p$^{+}$/n$^{+}$-diffusion in the n-well as a control gate instead of the second poly-silicon. The program and erase characteristics of the single-poly EEPROM were verified using the two-dimensional device simulator, MEDICI. The single-poly EEPROM was fabricated using 0.8$\mu$m ASIC CMOS process, and its CHE programming characteristics were measured using HP4155 parameteric analyzer and HP8110 pulse gnerator. Especially we investigated the CHE programming characteristics of the single-poly EEPROM with the p$^{+}$-diffusion or n$^{+}$-diffusion in the n-well as a control gate and the LDD or single-drain structure. The single-poly EEPROM with p$^{+}$-diffusion in the n-well as a control gate and single-drain structure was programmed to about VT$\thickapprox$5V with VDS=6V, VCG=12V(1ms pulse width).th).