• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.7
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• pp.18-27
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• 1997

A CMOS 950 MHz frequency synthesizer is designed and fabricated in a 0.8.mu.m standard CMOS process for IS-95-A CDMA mobile communication transceivers To utilize a CMOS ring VCO in a CDMA wireless communication receisver, we employed a QDC (quasi-direct conversion) receiver architecture for CDMA applications. Realized RF frequency synthesizer used as the RF local oscillator for a QDC receiver exhibits a phase noise of -92 dBc/Hz at 885kHz offset from the 950.4 MHz carrier, which complies with IS-95-A CDMA specification. It has a rms jitter of 23.7 ps, and draws 30mA from a 5V supply. Measured I/Q phase error of the 950.4 output signals is 0.7 degree.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.1
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• pp.88-95
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• 2013

We propose a novel driver circuit design using $0.18{\mu}m$ CMOS process technology that drives a 1550 nm high-speed VCSEL used in optical transceiver. We report a distinct improvement in bandwidth, voltage gain and eye diagram at 3.1Gb/s data rate in comparison with existing topology. In this paper, the design and layout of a 3.1Gb/s VCSEL driver for optical transceiver having arrayed multi-channel of integrating module is confirmed.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.983-986
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• 2003

This paper describes a 2.5V 80dB 360MHz CMOS VGA. A new variable degeneration resistor is proposed where the dc voltage drop over the degeneration resistor is minimized and employed in designing a low-voltage and high-speed CMOS VGA. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than 1.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$$\times$360${\mu}{\textrm}{m}$.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.7
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• pp.23-29
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• 1997

The performance degradation of CMOS differential amplifiers due to hot carrier effect has been measured and analyzed. Two-state CMOS amplifiers whose input transistors are PMOSFETs were designed and fabriacted using the ISRC CMOS 1.5.mu.m process. It was observed after the amplifier was hot-carrier stressed that the small-signal voltage gain and the input offset voltage increased and the phase margin decreased. The performance variation results from the increase of the transconductances and gate capacitances of the PMOSFETs used as input transistors in the differential input stage and the output stage and also resulted from the decrease of their output conductances. After long-term stress, the amplifier became unstable. The reason might be that its phase margin was reduced due to hot carrier effect.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.1
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• pp.17-22
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• 2001

The floating-gate MOSFETs were fabricated by employing 1.5 m n-well CMOS process and their optical-electrical properties were characterized for the application to CMOS image sensor system. Based on the simulation of energy band diagram and operating mechanism of parasitic BJT were proposed as solutions for the increase of photo-current value. In order to realize them, MOSFETs having multi-gate and channel structures were fabricated and 60% increase in photo-current was achieved through enlargement of depletion layer and parallel connection of parasitic BJTs by channel division.

• ETRI Journal
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• v.33 no.3
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• pp.393-400
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• 2011

A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 ${\mu}m$ CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 ${\mu}W$).

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.5
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• pp.753-756
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• 2012

In this paper, a modified low-votlage CMOS bandgap voltage reference with CTAT compensation is presented. The proposed structure doesn't use PTAT current. The proposed structure is more simple than the existing structure and doesn't use the eighteen BJT. The modified low-votlage CMOS bandgap voltage reference with CTAT compensation has been successfully verified in a standard 0.18um CMOS process. The simulation results have confirmed that, with the minimum supply voltage of 1.25V, the output reference voltage at 549mV has a temperature coefficient of 12$ppm/^{\circ}C$ from $0^{\circ}C$ to $100^{\circ}C$.

• Journal of Sensor Science and Technology
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• v.19 no.6
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• pp.469-474
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• 2010

This paper presents a 10Gbps CMOS parallel-to-serial converter for transmission of sensor data. A low-noise clock multiplying unit(CMU) and a multiplexer with controllable data sequence are proposed. The transmitter was fabricated in 0.13 um CMOS process and the measured total output jitter was less than 0.1 UIpp(unit-interval, peak-to-peak) over 20 kHz to 80 MHz bandwidth. The jitter of the CMU output only was measured as 0.2 ps,rms. The transmitter dissipates less than 200 mW from 1.5 V/2.5 V power supplies.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.1
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• pp.17-21
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• 2019

In this paper, a high precision straightness measurement system has been developed at low cost using a visible laser and CMOS image sensor. CMOS image sensor detected optical image and the variation of straightness was calculated by image processing. We have observed that the error of the developed straightness measurement system was 0.9% when a distance of 3m between laser and image sensor. And it can be applied to 3D printer and any other areas.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.2
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• pp.304-309
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• 2019

This paper presents a CMOS RF-to-DC converter for video surveillance disposable IoT applications. It widely harvests RF energy of 3G/4G cellular low-band frequency range by employing a tunable impedance matching network. The proposed converter consists of the differential-drive cross-coupled rectifier and the matching network with a 4-bit capacitor array. The proposed converter is designed using 130-nm standard CMOS process. The designed energy harvester can rectify the RF signals from 700 MHz to 900 MHz. It has a peak RF-to-DC conversion efficiency of 72.25%, 64.97%, and 66.28% at 700 MHz, 800 MHz, and 900 MHz with a load resistance of 10kΩ, respectively.