• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1460-1462
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• 1994

BiCMOS is the newly developed technology that integrates both CMOS and bipolar structures on the same integrated circuit. Improved performance can be obtained from combining the advantages of high density and low power in CMOS with the speed and current capibility advantages by bipolar. However, the major drawbacks to BiCMOS are high cost, long fabrication time and difficulty of merging CMOS with bipolar without degrading of device Performance because CMOS and bipolar share same process step. In this paper, N-Well CMOS oriented BiCMOS process and optimization of device performance are studied when N-Well links CMOS with bipolar process step by 2D process and 3D Device simulation. From the simulation, Constriction of linking process step has been understood and provided to give the method of choosing BiCMOS for various analog design request.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.136-141
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• 1996

In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.

• Journal of IKEEE
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• v.23 no.1
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• pp.326-329
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• 2019

Gallium nitride(GaN) has been a superior candidate for the next generation power electronics. As GaN-on-Si substrate technology is mature, there has been new demand for monolithic integration of GaN technology with Si CMOS devices. In this work, (110)Si CMOS process was developed and the fabricated devices were evaluated in order to confirm the feasibility of utilizing domestic foundry facility for monolithic integration of Si CMOS and GaN power devices.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.202-211
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• 2000

Utilizing the circuit simulator SPICE, we designed a 1.9GHz CMOS up-conversion mixer and explained in detail the simulation procedures including device modeling for the circuit design. Since the measured characteristics of the chip fabricated using the $0.5{\mu}m$ standard CMOS process had shown a big deviation from the characteristics expected by the original simulations, we tried to figure out the proper reasons for the discrepancies. Simulations considering the discovered problems in the original simulations have shown the validity of the simulation method tried for the design. We have shown that the utilized standard CMOS process can be used for the implementation of the chip characteristics similar to those of the equivalent chip fabricated using the GaAs MESFET process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.788-791
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• 2010

We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.

• Journal of information and communication convergence engineering
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• v.7 no.2
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• pp.215-218
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• 2009

In this paper, temperature stable current and voltage references using simple CMOS bias circuit are proposed. To obtain temperature stable characteristics of bias circuit a bandgap reference concept is used in a conventional circuit. The parasitic bipolar transistors or MOS transistors having different threshold voltage are required in a bandgap reference. Thereby the chip area increase or the extra CMOS process is required compared to a standard CMOS process. The proposed reference circuit can be integrated on a single chip by a standard CMOS process without the extra CMOS process. From the simulation results, the reference current variation is less than ${\pm}$0.44% over a temperature range from - $20^{\circ}C$ to $80^{\circ}C$. And the voltage variation is from - 0.02% to 0.1%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.91-92
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• 2005

The electromagnetic coupling effect in standard CMOS process is simulated and evaluated. EM coupling transfer characteristic between planar spiral inductors by isolation methode in standard CMOS have simulated and measured. Measurement results show that suppression of EM coupling effect by ground guardring. The evaluated structures are fabricated 1P5M(one poly, five metal) 0.25um standard CMOS process. These measurement results provide a isolation design guidelines in standard CMOS process for Rf coupling suppression.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.189-196
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• 1989

In this paper, BICMOS gate array technology that has CMOS devices for logic applications and bipolar devices for driver applications is presented. An optimized poly gate p-well CMOS process is chosen to fabricate the BICMOS gate array system and the basic concepts to design these devices are to improve the characteristics of bipolar & CMOS device with simple process technology. As the results hFE value is 120(Ic=1mA) for transistor, and there is no short channel effects for CMOS devices which have Leff to 1.25um and 1.35um for n-channel, respectively, 0.8nx gate delay time of 41 stage ring oscillators is obtained.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.2
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• pp.146-153
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• 2008

Integrated humidity sensor system with two stages operational amplifier has been designed and fabricated by $0.8{\mu}m$ analog mixed CMOS technology. The system (28 pin and $2mm{\times}4mm$) consisted of Wheatstone-bridge type humidity sensor, resistive type humidity sensor, temperature sensors and operational amplifier for signal amplification and process in one chip. The poly-nitride etch stop process has been tried to form the sensing area as well as trench in a standard CMOS process. This modified technique did not affect the CMOS devices in their essential characteristics and gave an allowance to fabricate the system on same chip by standard process. The operational amplifier showed the stable operation so that unity gain bandwidth was more than 5.46 MHz and slew rate was more than 10 V/uS, respectively. The drain current of n-channel humidity sensitive field effect transistor (HUSFET) increased from 0.54 mA to 0.68 mA as the relative humidity increased from 10 to 70 %RH.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.917-925
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• 2016

Schmitt Trigger logic is a gate level design method to have hysteresis characteristics to improve noise immunity in digital circuits. Dynamic Threshold voltage MOS(DTMOS) Schmitt trigger circuits can improve noise immunity without adding additional transistors but by controlling substrate bias. The performance of DTMOS Schmitt trigger logic has not been verified yet in standard CMOS process through measurement. In this paper, DTMOS Schmitt trigger logic was implemented and verified using Magna $0.18{\mu}m$ MPW process. DTMOS Schmitt trigger buffer, inverter, NAND, NOR and simple digital logic circuits were made for our verification. Hysteresis characteristics, power consumption, and delay were measured and compared with common CMOS logic gates. EM Immunity enhancement was verified through Direct Power Injection(DPI) noise immunity test method. DTMOS Schmitt trigger logics fabricated using CMOS process showed a significantly improved EM Immunity in 10 M~1 GHz frequency range.