• Journal of Sensor Science and Technology
• /
• v.30 no.4
• /
• pp.223-228
• /
• 2021

This work presents a low-power CMOS image sensor (CIS) with a multi-column-parallel (MCP) readout structure while focusing on improving its performance compared to previous works. A delta readout scheme that utilizes the image characteristics is optimized for the MCP readout structure. By simply alternating the MCP readout direction for each row selection, additional memory for the row-to-row delta readout is not required, resulting in a reduced area of occupation compared to the previous work. In addition, the bias current of a pre-amplifier in a successive approximate register (SAR) analog-to-digital converter (ADC) changes according to the operating period to improve the power efficiency. The prototype CIS chip was fabricated using a 0.18-㎛ CMOS process. A 160 × 120 pixel array with 4.4 ㎛ pitch was implemented with a 10-bit SAR ADC. The prototype CIS demonstrated a frame rate of 120 fps with a total power consumption of 1.92 mW.

• Journal of Sensor Science and Technology
• /
• v.23 no.2
• /
• pp.87-93
• /
• 2014

In this paper, we propose a block-based low-power complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a simple pixel structure for power efficiency. This method, which uses an additional computation circuit, makes it possible to reduce the power consumption of the pixel array. In addition, the computation circuit for a block-based CIS is very flexible for various types of pixel structures. The proposed CIS was designed and fabricated using a standard CMOS 0.18 ${\mu}m$ process, and the performance of the fabricated chip was evaluated. From a resultant image, the proposed block-based CIS can calculate a differing contrast in the block and control the operating voltage of the unit blocks. Finally, we confirmed that the power consumption in the proposed CIS with a simple pixel structure can be reduced.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.2
• /
• pp.20-27
• /
• 2011

A CMOS Image Sensor(CIS) mounted on mobile appliances always needs a low power consumption because of the battery life cycle. In this paper, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination, a low power single slope A/D converter with a novel comparator, and etc. Based on 0.13um CMOS process, the chip satisfies QVGA resolution($320{\times}240$ pixels) whose pitch is 2.25um and whose structure is 4-Tr active pixel sensor. From the experimental results, the ADC in the middle of CIS has a 10-b resolution, the operating speed of CIS is 16 frame/s, and the power dissipation is 25mW at 3.3V(Analog)/1.8V(Digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption is reduced approximately by 22% in sleep mode, 20% in operating mode.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.4
• /
• pp.270-274
• /
• 2006

A color filter array (CFA) helps a single electrical image sensor to recognize color images. The Red-Green-Blue (RGB) Bayer CFA is commonly used, but the amount of the light which arrives at the photodiode is attenuated with this CFA. Red-White-Blue (RWB) CFA increases the amount of the light which arrives at photodiode by using White (W) pixels instead of Green (G) pixels. However, white pixels are saturated earlier than red and blue pixels. The pseudo multiple capture scheme and the corresponding RWB CFA were proposed to overcome the early saturation problem of W pixels. The prototype CMOS image sensor (CIS) was fabricated with $0.35-{\mu}m$ CMOS process. The proposed CIS solves the early saturation problem of W pixels and increases the dynamic range.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.35 no.5
• /
• pp.460-465
• /
• 2007

This paper deals with the Fine Digital Sun Sensor (FDSS) for Science & Technology Satellite 2(STSAT-2). The FDSS was firstly developed by using CMOS-Image sensor(CIS) in South Korea. This paper will describe the configuration of the FDSS, the design of the optical part, the analysis result of the optical characteristics of the sunlight, and the calibration result measured by solar simulator.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.8 no.3
• /
• pp.513-521
• /
• 2007

Recently, camera function is one of the most primary functions out of the multimedia capabilities in the small mobile terminals. But, it has been difficult for implementing embedded devices with low cost because of not supporting camera interface in many SoCs. Thus, this paper presents a method of supporting camera function with ease for embedded devices which has not camera interface. For this purpose, the interface is implemented for a CMOS image sensor. The method is also provided that CIS(CMOS Image Sensor) is supported in the embedded system by programming the device driver.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.5
• /
• pp.50-57
• /
• 2008

In this paper, a high-efficiency charge pump for use in CMOS image sensor(CIS) is proposed. The proposed charge pump pursues high pumping efficiency by minimizing the switching and reversion losses by taking advantage of operation characteristics of CIS. That is, the proposed charge pump minimizes the switching loss by dynamically controlling the size of clock driver, pumping capacitor, and charge transfer switch based on the operation phase of CIS pixel sensor. The charge pump also minimizes the reversion loss by guaranteeing a sufficient non-overlapping period of local clocks using a tri-state local clock driver adapting the schmitt trigger. Comparison results using a 0.13-um CMOS process technology indicate that the proposed charge pump achieves up to 49.1% reduction on power consumption under no loading current condition as compared to conventional charge pump. They also indicate that the charge pump provides 19.0% reduction on power consumption under the maximum loading current condition.

• Journal of Sensor Science and Technology
• /
• v.26 no.2
• /
• pp.85-90
• /
• 2017

A wide dynamic range (WDR) CMOS image sensor (CIS) was developed with a specialized readout architecture for realizing high-sensitivity (HS) and low-sensitivity (LS) reading modes. The proposed pixel is basically a three-transistor (3T) active pixel sensor (APS) structure with an additional transistor. In the developed WDR CIS, only one mode between the HS mode for relatively weak light intensity and the LS mode for the strong light intensity is activated by an external controlling signal, and then the selected signal is read through each column-parallel readout circuit. The LS mode is implemented with the column capacitors and a feedback structure for adjusting column capacitor size. In particular, the feedback circuit makes it possible to change the column node capacitance automatically by using the incident light intensity. As a result, the proposed CIS achieved a wide dynamic range of 94 dB by synthesizing output signals from both modes. The prototype CIS is implemented with $0.18-{\mu}m$ 1-poly 6-metal (1P6M) standard CMOS technology, and the number of effective pixels is 176 (H) ${\times}$ 144 (V).

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.739-742
• /
• 2005

In this paper, an efficient detection algorithm for the flicker, which is caused by mismatching between light frequency and exposure time at CMOS image sensor (CIS), is proposed. The flicker detection can be implemented by specific hardware or complex signal processing logic. However it is difficult to implement on single chip image sensor, which has pixel, CDS, ADC, and ISP on a die, because of limited die area. Thus for the flicker detection, the simple algorithm and high accuracy should be achieved on single chip image sensor,. To satisfy these purposes, the proposed algorithm organizes only simple operation, which calculates the subtraction of horizontal luminance mean between continuous two frames. This algorithm was verified with MATLAB and Xilinx FPGA, and it is implemented with Magnachip 0.18 standard cell library. As a result, the accuracy is 95% in average on FPGA emulation and the consumed gate count is about 7,500 gates (@40MHz) for implementation using Magnachip 0.18 process.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.2
• /
• pp.239-247
• /
• 2007

In this paper, we propose a system that the Linux is ported in embedded system with peripheral devices of CIS(CMOS Image Sensor) and GPS module. The system acquires GGA sentence from GPS module by recognizing camera and GPS is used module in Linux kernel. And then the received location information is used to include still image acquired through CIS According to this paper, We compose hardware for embedded system, attach board (including camera), port Linux BootLoader and Kernel. And. then we realize that it insert kernel in CIS control device driver and GPS module device driver.