• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.15 no.7
• /
• pp.628-637
• /
• 1990

In this paper we present on architecture for a high sppeed CMOS multiplier which can be used for real-time digital signal processing. And a synthesis method for designing highly parallel algorithms in VLSI is presented. A parallel multiplier design based on the modified Booth's algorithms and Ling's algorthm. This paper addresses the design of multiplier capable of accpting data in 2's complement notation and coefficients in 2's complement notation. Multiplier consists of an interative array of sequential cells, and are well suited to VLSI implementation as a results of their modularity and regularity. Booth's decoders can be fully tested using a relatively small number af test vector.

• Journal of Power Electronics
• /
• v.14 no.4
• /
• pp.796-805
• /
• 2014

A digital controller with a low-power approach for point-of-load synchronous buck converters is discussed and compared with its analog counterpart to confirm its feasibility for system integration. The tri-mode digital controller IC in $0.35{\mu}m$ CMOS process is presented to demonstrate solutions that include a PID, quarter PID, and robust RST compensators. These compensators address the steady-state, stand-by, and transient modes according to the system operating point. An idle-tone free condition for ${\Sigma}-{\Delta}$ DPWM reduces the inherent tone noise under DC-excitation. Compared with that of the traditional approach, this condition generates a quasi-pure modulation signal. Experimental results verify the closed-loop performances and confirm the power-saving mechanism of the proposed controller.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.1862-1863
• /
• 2007

Testing the analog/mixed-signal circuitry of a mixed-signal IC has become a difficult task. Offset error, gain error, Non-monotonic behavior, Differential Non-linearity(DNL) error, Integral Non-linearity(INL) error are important specifications used as test parameters for DAC. In this paper, we propose an efficient BIST structure for DAC testing. The proposed BIST adds the circuit which uses the capacitor and op-amp, and accomplishes a test.

• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.894-897
• /
• 2003

Recently, the rapid growth of mobile radio system has led to an increasing demand of low-cost high performance communication IC's. In this paper, we have designed RF front end for wireless LAN receiver employ zero-IF architecture. A low-noise amplifier (LNA) and double-balanced mixer is included in a front end. The zero-IF architecture is easy to integrate and good for low power consumption, so that is coincided to requirement of wireless LAN. But the zero-IF architecture has a serious problem of large offset. Image-reject mixer is a good structure to solve offset problem. Using offset compensation circuit is good structure, too. The front end is implemented in 0.25 ${\mu}m$ CMOS technology. The front end has a noise figure of 5.6 dB, a power consumption of 16 mW and total gain of 22 dB.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.1121-1124
• /
• 2002

In this paper, an IC realization of a cell-network type SC DC-DC converter is reported. To achieve small and low-cost realization, the converter is designed by using a 1.2 $\mu\textrm{m}$ CMOS technology. The CMOS implemented converter will be useful as a building block of various mobile equipments since step-up and step-down voltages can be provided at one time. Concerning the proposed DC-DC converter, SPICE simulatiorls are performed to investigate the characteristics of the circuit. The SPICE simulations show that, the efficiency of the simulated circuit is more than 95 %. From the layout design using a CAD tool, MAGIC, the VLSI chip is fabricated in the chip fabrication program of VLSI Design and Education Center(VDEC), the University of Tokyo with the collaboration by On-Semiconductor. The proposed circuit is integrable by a standard 1.2 $\mu\textrm{m}$ CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.15 no.8
• /
• pp.639-647
• /
• 1990

Dynamic time warp(DTW) needs for interative calculations and the design of PE cell suitable for the operations is very important. Accordingly, this paper aims at the real time recognition design which enables large dictionary hardware realization using DTW algorithm. The DTW PE cell is seperated into three large blocks. "MIN" is the one block for counting accumulated minimum distance, "ADD" block calculates these minimum distances, and "ABS" seeks for the absolute values to the total sum of local distances. We have accomplisehd circuit design and verification for the MIN blocks, and performed MIN layout and DRC(design rule check) using 3um CMOS N-Well rule base.ing 3um CMOS N-Well rule base.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.15 no.8
• /
• pp.648-658
• /
• 1990

There are many methods for speed up counting in speech recongition. A multiple processing method is the one way to achieve the aim using systolic array. This arithmetic operation by the array is achieved pipelining skill. And the operation is multiprocessing by processing element(PE) that is incresing counting efficiencies. The DTW PE cell is seperated into three large blocks. "MIN" is the one block for counting accumulated minimum distance, "ADD" block calculated these minimum distances, and "ABS" seeks for the absolut values to the total sum of local distances. We have accomplished circuit design and verification about the "ADD" and "ABS" blocks, and performed total layout '||'&'||' DRC(design rule check) using 3um CMOS N-Well rule base.le check) using 3$\mu$m CMOS N-Well rule base.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.11a
• /
• pp.167-170
• /
• 2002

The influence of Si surface damage on Ni-silicide with TiN Capping layer and the effect of $H_2$ anneal are characterized. Si surface is intentionally damaged using Ar Sputtering. The sheet resistance of NiSi formed on damaged silicon increased rapidly as Ar sputtering time increased. However, the thermal stability of Ni-Si on the damage silicon was more stable than that on at undamaged Si, which means that damaged region retards the formation of NiSi. It was shown that $H_2$ anneal and TiN capping is highly effective in reducing NiSi sheet resistance.

• ETRI Journal
• /
• v.40 no.6
• /
• pp.693-698
• /
• 2018

This paper presents a true-time delay (TTD) using a commercial $0.13-{\mu}m$ CMOS process for wideband phased-array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers (WDGAs), a 7-bit TTD circuit, and a 6-bit digital step attenuator (DSA) circuit. The T-type attenuator with a low-pass filter and the WDGAs are implemented for a low insertion loss error between the reference and time-delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB, respectively, at 2 GHz-18 GHz. The maximum time delay of 198 ps with a 1.56-ps step and the maximum attenuation of 31.5 dB with a 0.5-dB step are achieved at 2 GHz-18 GHz. The RMS time-delay and amplitude errors are <3 ps and <1 dB, respectively, at 2 GHz-18 GHz. An output P1 dB of <-0.5 dBm is achieved at 2 GHz-18 GHz. The chip size is $3.3{\times}1.6mm^2$, including pads, and the DC power consumption is 370 mW for a 3.3-V supply voltage.

• ETRI Journal
• /
• v.31 no.5
• /
• pp.622-624
• /
• 2009

This letter presents a compact 2.5 Gb/s burst-mode receiver using the first reported monolithic amplifier IC developed with 0.25 ${\mu}m$ SiGe BiCMOS technology. With optimum avalanche photodiode gain, the receiver module can obtain a fast response, high sensitivity and wide dynamic range, satisfying the overhead timing and various power specifications for a 2.5 Gb/s next-generation passive optical network (PON), as well as a legacy 1.25 Gb/s PON in the upstream.